Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 41
PIC16C745/765
FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h PORTD
(2)
Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE
(2)
— — — — —RE2RE1RE0---- -xxx ---- -uuu
89h TRISE
(2)
IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745. Always maintain these bits clear.
2: PIC16C765 only.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>