Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 27
PIC16C745/765
4.2.2.6 PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6: PERIPHERAL INTERRUPT ENABLE 2 REGISTER (PIE2: 8Dh)
4.2.2.7 PIR2 REGISTER
This register contains the CCP2 interrupt flag bit.
REGISTER 4-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused