Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 159
PIC16C745/765
Power-on Reset (POR)
Timing Diagram
....................................................... 136
PR2 Register
.............................................................. 18, 49
PRO MATE II Universal Programmer
........................... 123
Product Identification System
.......................................... 163
Program Counter
PCLATH Register
.................................................... 109
Program Memory
Paging
....................................................................... 29
Program Memory Maps
PIC16C745/765
......................................................... 15
Program Verification
........................................................ 112
PSPMODE bit
...................................................... 37, 38, 40
PUSH
................................................................................. 29
R
RBIF bit ..................................................................... 33, 109
RCREG
.............................................................................. 19
RCSTA Register
......................................................... 19, 78
RD
pin ................................................................................ 40
Register File
...................................................................... 15
Registers
FSR
Summary
........................................................... 19
INDF
Summary
........................................................... 19
INTCON
Summary
........................................................... 19
PCL
Summary
........................................................... 19
PCLATH
Summary
........................................................... 19
PORTB
Summary
........................................................... 19
Reset Conditions
..................................................... 104
Special Function Register Summary
......................... 17
STATUS
Summary
........................................................... 19
TMR0
Summary
........................................................... 19
TRISB
Summary
........................................................... 20
Reset
........................................................................ 99, 101
Timing Diagram
....................................................... 136
Reset Conditions for Special Registers
........................... 104
RP0 bit
........................................................................ 15, 22
RP1 bit
............................................................................... 22
RX9 bit
............................................................................... 78
RX9D bit
............................................................................ 78
S
Serial Communication Interface (SCI) Module, See USART
Services
One-Time-Programmable (OTP)
................................. 7
Quick-Turnaround-Production (QTP)
.......................... 7
Serialized Quick-Turnaround Production (SQTP)
....... 7
SLEEP
...................................................................... 99, 101
Software Simulator (MPLAB-SIM)
................................... 122
SPBRG Register
................................................................ 18
Special Features of the CPU
............................................. 99
Special Function Registers
................................................ 17
PIC16C745/765
......................................................... 17
SPEN bit
............................................................................ 78
SREN bit
............................................................................ 78
SSPBUF
............................................................................ 19
Stack
.................................................................................. 29
Overflows
.................................................................. 29
Underflow
.................................................................. 29
Status
................................................................................ 64
STATUS Register
..................................................... 22, 109
Synchronous Serial Port Module
....................................... 57
T
T1CKPS0 bit ..................................................................... 45
T1CKPS1 bit
..................................................................... 45
T1CON
.............................................................................. 20
T1CON Register
......................................................... 19, 45
T1OSCEN bit
.................................................................... 45
T1SYNC
bit ....................................................................... 45
T2CKPS0 bit
..................................................................... 49
T2CKPS1 bit
..................................................................... 49
T2CON Register
......................................................... 19, 49
T
AD .................................................................................... 96
Timer0
RTCC
...................................................................... 105
Timing Diagram
....................................................... 137
Timer1
Timing Diagram
....................................................... 137
Timers
Timer0
....................................................................... 43
External Clock
................................................... 44
Interrupt
............................................................. 43
Prescaler
........................................................... 44
Prescaler Block Diagram
.................................. 43
T0CKI
................................................................ 44
T0IF
................................................................. 109
TMR0 Interrupt
................................................ 109
Timer1
Asynchronous Counter Mode
........................... 47
Capacitor Selection
........................................... 47
Operation in Timer Mode
.................................. 46
Oscillator
........................................................... 47
Prescaler
........................................................... 47
Resetting of Timer1 Registers
.......................... 47
Resetting Timer1 using a CCP
Trigger Output
................................................... 47
Synchronized Counter Mode
............................ 46
T1CON
.............................................................. 45
TMR1H
.............................................................. 47
TMR1L
.............................................................. 47
Timer2
Block Diagram
................................................... 49
Module
.............................................................. 49
Postscaler
......................................................... 49
Prescaler
........................................................... 49
T2CON
.............................................................. 49
Timing Diagrams
USART Asynchronous Master Transmission
............ 82
USART Asynchronous Reception
............................. 83
USART Synchronous Reception
............................... 88
USART Synchronous Transmission
.......................... 86
Wake-up from Sleep via Interrupt
.................. 108, 112
Timing Diagrams and Specifications
............................... 133
A/D Conversion
....................................................... 142
Brown-out Reset (BOR)
.......................................... 136
Capture/Compare/PWM (CCP)
............................... 138
CLKOUT and I/O
..................................................... 135
External Clock
......................................................... 133
Oscillator Start-up Timer (OST)
.............................. 136
Parallel Slave Port (PSP)
........................................ 139
Power-up Timer (PWRT)
......................................... 136
Reset
....................................................................... 136
Timer0 and Timer1
.................................................. 137
USART Synchronous Receive (Master/Slave)
........ 140