Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 15
PIC16C745/765
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16C745/765 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. All devices covered by this data sheet have 8K
x 14 bits of program memory. The address range is
0000h - 1FFFh for all devices.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC16C745/765 PROGRAM
MEMORY MAP AND STACK
4.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
RP<1:0> (STATUS<6:5>)
= 00  Bank0
= 01  Bank1
= 10  Bank2
= 11  Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All implemented banks contain SFRs. Some “high use”
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indi-
rectly through the File Select Register (FSR)
(Section 4.5).
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
Page 2
1800h
17FFh
Page 3
1FFFh