Datasheet

PIC16C745/765
DS41124D-page 142 Preliminary  1999-2013 Microchip Technology Inc.
FIGURE 16-13: A/D CONVERSION TIMING
TABLE 16-11: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(T
OSC/2) (1)
7 6 5432 10
Note: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
134
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
130 T
AD A/D clock period 1.6 — — sTOSC based, VREF  3.0V
2.0 — — sT
OSC based,
2.5V V
REF  5.5V
2.0 4.0 6.0 s A/D RC Mode
131 T
CNV Conversion time (not including S/H time)
(Note 1)
11 — 11 TAD
132 TACQ Acquisition time 5* — — s The minimum time is the ampli-
fier settling time. This may be
used if the “new” input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on C
HOLD).
134 T
GO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is
selected as RC, a time of T
CY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 T
SWC Switching from convert  sample time 1.5 — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 12.1 for minimum conditions.