Datasheet

PIC16C745/765
DS41124D-page 140 Preliminary  1999-2013 Microchip Technology Inc.
FIGURE 16-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 16-8: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 16-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 16-9: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
120* T
CKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
——80 ns
121* T
CKRF Clock out rise time and fall time (Master mode) — — 45 ns
122* T
DTRF Data out rise time and fall time — — 45 ns
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
125* T
DTV2CKL SYNC RCV (MASTER & SLAVE)
Data setup before CK  (DT setup time)
15 — — ns
126* T
CKL2DTL Data hold after CK  (DT hold time) 15 — — ns
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note: Refer to Figure 16-2 for load conditions.
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 16-2 for load conditions.
125
126
RC6/TX/CK pin
RC7/RX/DT pin