Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 139
PIC16C745/765
FIGURE 16-10: PARALLEL SLAVE PORT TIMING (PIC16C765)
TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS
Note: Refer to Figure 16-2 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD<7:0>
62
63
64
65
Param No. Sym Characteristic Min Typ† Max Units Conditions
62* T
DTV2WRH Data in valid before WR or CS (setup time) 20 — — ns
63* T
WRH2DTIWR or CS to data–in invalid (hold time) 20 — — ns
64 T
RDL2DTVRD and CS to data–out valid — — 80 ns
65* T
RDH2DTIRD or CS to data–out invalid 10 — 30 ns
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: PIC16C765 only.