Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 135
PIC16C745/765
FIGURE 16-5: CLKOUT AND I/O TIMING
TABLE 16-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
10* T
OSH2CKLOSC1 to CLKOUT — 75 200 ns Note 1
11* T
OSH2CKHOSC1 to CLKOUT — 75 200 ns Note 1
12* T
CKR CLKOUT rise time — 35 100 ns Note 1
13* T
CKF CLKOUT fall time — 35 100 ns Note 1
14* T
CKL2IOVCLKOUT  to Port out valid — — 0.5 TCY + 20 ns Note 1
15* T
IOV2CKH Port in valid before CLKOUT  TOSC + 200 — — ns Note 1
16* T
CKH2IOI Port in hold after CLKOUT  0 — — ns Note 1
17* T
OSH2IOVOSC1 (Q1 cycle) to Port out valid — 50 150 ns
18* T
OSH2IOIOSC1 (Q2 cycle) to Port input invalid (I/O in hold
time)
100 — — ns
19* T
IOV2OSH Port input valid to OSC1(I/O in setup time) 0 — — ns
20* T
IOR Port output rise time — 10 40 ns
21* T
IOF Port output fall time — 10 40 ns
22††* T
INP INT pin high or low time TCY ——ns
23††* T
RBP RB<7:4> change INT high or low time
T
CY ——ns
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x T
OSC.
2: F
INT = OSC1 when PLL is disabled.
Note: Refer to Figure 16-2 for load conditions.
FINT
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
old value
new value