Datasheet

PIC16C745/765
DS41124D-page 134 Preliminary  1999-2013 Microchip Technology Inc.
TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
1A F
OSC External CLKIN Frequency
(Note 1)
24 — 24 MHz EC osc mode
6 — 6 MHz E4 osc mode
Oscillator Frequency
(Note 1)
24 — 24 MHz HS osc mode
6 — 6 MHz H4 osc mode
1T
OSC External CLKIN Period
(Note 1)
41 — 41 ns EC osc modes
167 — 167 ns E4 osc mode
Oscillator Period
(Note 1)
41 — 41 ns HS osc modes
167 — 167 ns H4 osc mode
2T
CY Instruction Cycle Time (Note 1) 167 — DC ns TCY = 4/FINT
3* TOSL,
T
OSH
External Clock in (OSC1) High or Low
Time
10 — — ns EC oscillator
4* T
OSR,
T
OSF
External Clock in (OSC1) Rise or Fall
Time
— — 15 ns EC oscillator
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time-base period when the PLL is enabled, or the input
oscillator time-base period divided by 4 when the PLL is disabled. All specified values are based on characterization data
for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these
specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices
are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input
is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.