Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 133
PIC16C745/765
16.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 16-3: EXTERNAL CLOCK TIMING
FIGURE 16-4: CLOCK MULTIPLIER (PLL) PHASE RELATIONSHIP
3
3
4
4
1
2
Q4
Q1 Q2 Q3 Q4
Q1
OSC1
CLKOUT
FINT
OSC1/
CLKIN
Note 1: FINT represents the internal clock signal. FINT equals FOSC or CLKIN if the PLL is disabled. FINT
equals 4x FOSC or 4x CLKIN if the PLL is enabled. TCY is always 4/FINT. FINT is OSC1 pin in EC
mode, PLL disabled.
2: FINT = OSC1 in EC mode with PLL disabled.