Datasheet

PIC16C745/765
DS41124D-page 110 Preliminary  1999-2013 Microchip Technology Inc.
13.8 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip dedi-
cated oscillator, which does not require any external
components. The WDT will run, even if the clock on the
OSC1/CLKIN and OSC2/CLKOUT pins of the device
has been stopped, for example, by execution of a
SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.8.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms
(parameter #31, T
WDT). The time-out periods vary with
temperature, V
DD and process variations. If longer
time-out periods are desired, a prescaler with a division
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEP instruction prevents the WDT from generat-
ing a RESET, but will allow the WDT to wake the device
from SLEEP mode.
The TO
bit in the STATUS register will be cleared upon
a WDT time-out.
13.8.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (V
DD = Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
FIGURE 13-7: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 13-8: SUMMARY OF WATCHDOG TIMER REGISTERS
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
All Other
Resets
2007h Config. bits
— BODEN
(1)
CP1 CP0 PWRTE
(1)
WDTE PLL FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
From TMR0 Clock Source
(Figure 6-1)
To TM R0 MU X
(Figure 6-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS<2:0>
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS<2:0> are bits in the OPTION register.
8