Datasheet

 1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 109
PIC16C745/765
13.6.1 INT INTERRUPT
The external interrupt on RB0/INT pin is edge trig-
gered: either rising, if bit INTEDG (OPTION_REG<6>)
is set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 13.9 for details on SLEEP mode.
13.6.2 TMR0 INTERRUPT
An overflow (FFh  00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 6.0)
13.6.3 PORTB INTERRUPT ON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 5.2).
13.7 Context Saving During Interrupts
During an interrupt, only the PC is saved on the stack.
At the very least, W and STATUS should be saved to
preserve the context for the interrupted program. All
registers that may be corrupted by the ISR, such as
PCLATH or FSR, should be saved.
Example 13-1 stores and restores the STATUS, W and
PCLATH registers. The register, W_TEMP, is defined in
Common RAM, the last 16 bytes of each bank that may
be accessed from any bank. The STATUS_TEMP and
PCLATH_TEMP are defined in bank 0.
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register in bank 0.
d) Executes the ISR code.
e) Restores the PCLATH register.
f) Restores the STATUS register
g) Restores W.
Note that W_TEMP, STATUS_TEMP and
PCLATH_TEMP are defined in the common RAM area
(70h - 7Fh) to avoid register bank switching during con-
text save and restore.
EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
#define W_TEMP 0x70
#define STATUS_TEMP 0x71
#define PCLATH_TEMP 0x72
org 0x04 ; start at Interrupt Vector
MOVWF W_TEMP ; Save W register
MOVF STATUS,W
MOVWF STATUS_TEMP ; save STATUS
MOVF PCLATH,W
MOVWF PCLATH_TEMP ; save PCLATH
:
(Interrupt Service Routine)
:
MOVF PCLATH_TEMP,W
MOVWF PCLATH
MOVF STATUS_TEMP,W
MOVWF STATUS
SWAPF W_TEMP,F ;
SWAPF W_TEMP,W ; swapf loads W without affecting STATUS flags
RETFIE
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.