Datasheet
1999-2013 Microchip Technology Inc. Preliminary DS41124D-page 103
PIC16C745/765
13.4 RESETS
13.4.1 POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
V
DD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR
pin
directly (or through a resistor) to V
DD. This will elimi-
nate external RC components usually needed to create
a POR. A maximum rise time for V
DD is specified. See
Electrical Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
startup conditions.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
13.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up from the POR. The PWRT oper-
ates on an internal RC oscillator. The device is kept in
RESET as long as the PWRT is active. The PWRT’s
time delay allows V
DD to rise to an acceptable level. A
configuration bit is provided to enable/disable the
PWRT.
The power-up time delay will vary from chip to chip due
to V
DD, temperature and process variation. See DC
parameters for details (T
PWRT, parameter #33).
13.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer provides a delay of 1024
oscillator cycles (from OSC1 input) after the PWRT
delay. This ensures that the crystal oscillator or resona-
tor has started and stabilized.
The OST time-out is invoked only for HS mode and
only on Power-on Reset or wake-up from SLEEP.
13.4.4 BROWN-OUT RESET (BOR)
If V
DD falls below VBOR (parameter D005) for longer
than T
BOR (parameter #35), the brown-out situation
will reset the device. If V
DD falls below VBOR for less
than T
BOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
T
PWRT (parameter #33). If VDD should fall below VBOR
during TPWRT, the Brown-out Reset process will
restart when V
DD rises above VBOR, with the Power-
up Timer Reset. Since the device is intended to oper-
ate at 5V nominal only, the Brown-out Detect is always
enabled and the device will RESET when Vdd falls
below the brown-out threshold. This device is unique
in that the 4WDT timer will not activate after a brown-
out if PWRTE
= 1 (inactive).
13.4.5 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled), when a Power-on
Reset occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (HS). When the OST ends,
the device comes out of RESET.
If MCLR
is kept low long enough, the time-outs will
expire. Bringing MCLR
high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16CXX device operating in
parallel.
Table 13-5 shows the RESET conditions for the STA-
TUS, PCON and PC registers, while Table 13-7 shows
the RESET conditions for all the registers.
13.4.6 POWER CONTROL/STATUS REGISTER
(PCON)
The Brown-out Reset Status bit, BOR
, is unknown on a
POR. It must be set by the user and checked on sub-
sequent RESETS to see if bit BOR
was cleared, indi-
cating a BOR occurred. The BOR
bit is not predictable
if the Brown-out Reset circuitry is disabled.
The Power-on Reset Status bit, POR, is cleared on a
POR and unaffected otherwise. The user must set this
bit following a POR and check it on subsequent
RESETS to see if it has been cleared.