PIC16C745/765 8-Bit CMOS Microcontrollers with USB Devices included in this data sheet: • PIC16C765 28-Pin DIP, SOIC Microcontroller Core Features: • High-performance RISC CPU • Only 35 single word instructions Memory Program x14 Data x8 Pins A/D Resolution A/D Channels PIC16C745 8K 256 28 8 5 PIC16C765 8K 256 40 8 8 Device • All single cycle instructions except for program branches which are two cycle • Interrupt capability (up to 12 internal/external interrupt sources) • Eight level de
RC6/TX/CK D+ DRD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 VUSB RC2/CCP1 RC1/T1OSI/CCP2 NC 44-Pin TQFP PIC16C765 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 PIC16C765 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4 RA4/T0CKI NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RC1/T1OSI/CCP2 RC2/CCP1 VUSB RD0/PSP0 RD1/PSP1 RD2/PSP2
PIC16C745/765 Table of Contents 1.0 General Description .............................................................................................................................................. 5 2.0 PIC16C745/765 Device Varieties ......................................................................................................................... 7 3.0 Architectural Overview .............................................................................................................................
PIC16C745/765 NOTES: DS41124D-page 4 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 1.0 GENERAL DESCRIPTION The PIC16C745/765 devices are low cost, high-performance, CMOS, fully-static, 8-bit microcontrollers in the PIC16CXX mid-range family. All PIC® microcontrollers employ an advanced RISC architecture. The PIC16C745/765 microcontroller family has enhanced core features, eight-level deep stack and multiple internal and external interrupt sources.
PIC16C745/765 NOTES: DS41124D-page 6 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 2.0 PIC16C745/765 DEVICE VARIETIES 2.3 A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C745/765 Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. 2.
PIC16C745/765 NOTES: DS41124D-page 8 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C745/765 family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C745/765 uses a Harvard architecture, in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus.
PIC16C745/765 FIGURE 3-1: PIC16C745/765 BLOCK DIAGRAM 13 Program Memory Program Bus RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4 RAM File Registers 256 x 8 8 Level Stack (13 bit) 8K x 14 PORTA 8 Data Bus Program Counter EPROM 14 RAM Addr(1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB<7:1> FSR reg STATUS reg 8 PORTC 3 Power-up Timer Instruction Decode & Control OSC1/ CLKIN OSC2/ CLKOUT Timing Generation x4 PLL Oscillator Start-up Timer RC0/
PIC16C745/765 TABLE 3-1: PIC16C745/765 PINOUT DESCRIPTION Name MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI Function Input Type Output Type MCLR ST — Master Clear VPP Power — Programming Voltage OSC1 Xtal — Crystal/Resonator CLKIN ST — External Clock Input OSC2 — Xtal CLKOUT — CMOS Internal Clock (FINT/4) Output RA0 ST CMOS Bi-directional I/O AN0 AN — RA1 ST CMOS AN1 AN — RA2 ST CMOS AN2 AN — RA3 ST CMOS AN3 AN — VRE
PIC16C745/765 TABLE 3-1: PIC16C745/765 PINOUT DESCRIPTION (CONTINUED) Name RC6/TX/CK RC6 ST CMOS Bi-directional I/O TX — CMOS USART Async Transmit Description ST CMOS USART Master Out/Slave In Clock ST CMOS Bi-directional I/O RX ST — DT ST CMOS USART Data I/O RD0 TTL CMOS Bi-directional I/O(2) PSP0 TTL — RD1 TTL CMOS PSP1 TTL — RD2 TTL CMOS PSP2 TTL — RD3 TTL CMOS PSP3 TTL — RD4 TTL CMOS PSP4 TTL — RD5 TTL CMOS PSP5 TTL — RD6 TTL CMOS PSP6 T
PIC16C745/765 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input feeds either an on-chip PLL, or directly drives (FINT). The clock output from either the PLL or direct drive (FINT) is internally divided by four to generate four non-overlapping quadrature clocks namely, Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4.
PIC16C745/765 NOTES: DS41124D-page 14 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 4.0 MEMORY ORGANIZATION 4.2 4.1 Program Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 are the bank select bits. The PIC16C745/765 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. All devices covered by this data sheet have 8K x 14 bits of program memory. The address range is 0000h - 1FFFh for all devices.
PIC16C745/765 FIGURE 4-2: Bank 0 DATA MEMORY MAP FOR PIC16C745/765 File Address Bank 1 File Address Bank 2 File Address Bank 3 File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.
PIC16C745/765 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. TABLE 4-1: Address The Special Function Registers can be classified into two sets (core and peripheral).
PIC16C745/765 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 1 80h INDF(3) Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION 82h PCL(3) 83h STATUS 84h FSR(3) 85h TRISA 86h TRISB RBPU INTEDG T0CS T0SE PSA PS2 PS1 0000 0000 0000 0000 PS0 Program Counter's (PC) Least Significant Byte (3) IRP RP1
PIC16C745/765 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 2 100h INDF(3) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h (3) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h 104h PCL STATUS FSR (3) (3) IRP
PIC16C745/765 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 3 180h INDF(3) 181h OPTION_REG 182h PCL(3) 183h 184h STATUS FSR 185h 186h Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 0000 0000 0000 0000 PS0 Program Counter's (PC) Least Significant Byte (3) (3) — TRISB IRP
PIC16C745/765 TABLE 4-2: Address Name USB DUAL PORT RAM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PID1 DTS PID0 BSTALL — — — — 1A0h BD0OST UOWN UOWN DATA0/1 DATA0/1 PID3 — PID2 — 1A1h BD0OBC — — — — 1A2h BD0OAL 1A3h — Buffer Address Low — UOWN UOWN DATA0/1 DATA0/1 PID3 — PID2 — 1A5h BD0IBC — — — — 1A6h BD0IAL PID3 — PID2 — 1A9h BD1OBC — — — — 1AAh BD1OAL PID3 — PID2 — 1ADh BD1IBC — — — — 1AEh BD1IAL — — — — Byte Count xxxx xxxx uuuu uu
PIC16C745/765 4.2.2.1 STATUS REGISTER For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). The STATUS register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. It is recommended that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS register.
PIC16C745/765 4.2.2.2 OPTION REGISTER Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: R/W-1 RBPU To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16C745/765 4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C745/765 4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16C745/765 4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C745/765 4.2.2.6 PIE2 REGISTER This register contains the individual enable bit for the CCP2 peripheral interrupt. REGISTER 4-6: PERIPHERAL INTERRUPT ENABLE 2 REGISTER (PIE2: 8Dh) U-0 — bit7 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 CCP2IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: 4.2.2.
PIC16C745/765 4.2.2.8 PCON REGISTER Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 4-8: U-0 — U-0 — BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16C745/765 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 4-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16C745/765 4.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-2: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. movlw movwf clrf incf btfss goto NEXT Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h.
PIC16C745/765 5.0 I/O PORTS FIGURE 5-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Data Bus 5.1 WR Port PORTA and TRISA Registers PORTA is a 6-bit latch. BLOCK DIAGRAM OF RA<3:0> AND RA5 PINS D Q VDD Q CK P Data Latch The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output.
PIC16C745/765 TABLE 5-1: PORTA FUNCTIONS Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4 Legend: Output Type RA0 ST CMOS AN0 AN — RA1 ST CMOS AN1 AN — RA2 ST CMOS Description Bi-directional I/O A/D Input Bi-directional I/O A/D Input Bi-directional I/O AN2 AN — RA3 ST CMOS AN3 AN — VREF AN — A/D Positive Reference RA4 ST OD Bi-directional I/O T0CKI ST — RA5 ST A/D Input Bi-directional I/O A/D Input Timer 0 Clock Input Bi-directional I/O AN4 AN OD = o
PIC16C745/765 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>).
PIC16C745/765 TABLE 5-3: PORTB FUNCTIONS Function Input Type Output Type RB0 TTL CMOS INT ST — RB1 RB1 TTL CMOS Bi-directional I/O RB2 RB2 TTL CMOS Bi-directional I/O RB3 RB3 TTL CMOS Bi-directional I/O RB4 RB4 TTL CMOS Bi-directional I/O with Interrupt-on-Change RB5 RB5 TTL CMOS Bi-directional I/O with Interrupt-on-Change RB6 TTL CMOS Bi-directional I/O with Interrupt-on-Change Name RB0/INT RB6/ICSPC RB7/ICSPD Legend: Bi-directional I/O Interrupt ICSPC ST RB7 T
PIC16C745/765 5.3 PORTC and TRISC Registers FIGURE 5-5: PORTC is a 5-bit bi-directional port. Each pin is individually configureable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin.
PIC16C745/765 TABLE 5-5: PORTC FUNCTIONS Name RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 Function Input Type Output Type RC0 ST CMOS T1OSO — Xtal T1CKI ST — T1 Clock Input RC1 ST CMOS Xtal — T1 Oscillator Input CCP2 — — Capture In/Compare Out/PWM Out 2 Bi-directional I/O RC2 ST CMOS CCP1 — — RC6 ST CMOS Bi-directional I/O TX — CMOS USART Async Transmit CK ST CMOS USART Master Out/Slave In Clock RC7 ST CMOS Bi-directional I/O RX ST — RC7/RX/DT DT ST OD = o
PIC16C745/765 5.4 PORTD and TRISD Registers FIGURE 5-6: PORTD BLOCK DIAGRAM VDD Note: The PIC16C745 does not provide PORTD. The PORTD and TRISD registers are reserved. Always maintain these bits clear. Data Bus WR Port PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. D Q I/O pin CK Data Latch PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>).
PIC16C745/765 5.5 PORTE and TRISE Registers FIGURE 5-7: PORTE BLOCK DIAGRAM VDD Note 1: The PIC16C745 does not provide PORTE. The PORTE and TRISE registers are reserved. Always maintain these bits clear. Data Bus WR Port PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configured as inputs or outputs. These pins have Schmitt Trigger input buffers.
PIC16C745/765 REGISTER 5-1: PORTE DATA DIRECTION CONTROL REGISTER(1) (TRISE: 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a pr
PIC16C745/765 5.6 Note: Parallel Slave Port (PSP) The PIC16C745 does not provide a parallel slave port. The PORTD, PORTE, TRISD and TRISE registers are reserved. Always maintain these bits clear. PORTD operates as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode, it is asynchronously readable and writable by the external world through RD control input pin RE0/RD/AN5 and WR control input pin RE1/WR/AN6.
PIC16C745/765 FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-11: Address 08h 09h REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTD(2) Port data latch when written: Port pins when read PORTE (2) (2) — — — — — RE2
PIC16C745/765 NOTES: DS41124D-page 42 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 6.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2.
PIC16C745/765 6.2 Using Timer0 with an External Clock The PSA and PS<2:0> bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.
PIC16C745/765 7.0 TIMER1 MODULE In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>).
PIC16C745/765 7.1 Timer1 Operation in Timer Mode 7.2 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FINT. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS.
PIC16C745/765 7.3 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.1).
PIC16C745/765 TABLE 7-2: Address REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name 0Bh,8Bh, INTCON 10Bh, 18Bh Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) PSPIE ADIE RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Leas
PIC16C745/765 8.0 TIMER2 MODULE 8.1 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FINT/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS<1:0> (T2CON<1:0>). The Timer2 module has an 8-bit period register PR2.
PIC16C745/765 TABLE 8-1: Address Name 0Bh,8Bh, INTCON 10Bh,18Bh REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 PSPIF(1) 8Ch PIE1 (1) 11h TMR2 12h T2CON 92h PR2 Legend: Note 1: Value on all other resets Bit 6 PIR1 0Ch Value on: POR, BOR Bit 7 PSPIE ADIE RCIE TXIE USBIE CCP1IE TMR2IE 0000 0000
PIC16C745/765 9.0 CAPTURE/COMPARE/PWM MODULES CCP2 Module: Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit capture register • 16-bit compare register • PWM master/slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 9-1 and Table 9-2 show the resources and interactions of the CCP module(s).
PIC16C745/765 REGISTER 9-1: CAPTURE/COMPARE/PWM CONTROL REGISTER (CCP1CON: 17H, CCP2CON: 1Dh) U — bit7 U — R/W-0 DCnB1 R/W-0 R/W-0 DCnB0 CCPnM3 R/W-0 CCPnM2 R/W-0 R/W-0 CCPnM1 CCPnM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: DCnB<1:0>: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRnL.
PIC16C745/765 9.1 9.1.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 9.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 pin is configured as an output, a write to the port can cause a capture condition.
PIC16C745/765 9.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: Note: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits CCP1M<3:0> (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set.
PIC16C745/765 FIGURE 9-4: When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. PWM OUTPUT Period Maximum PWM resolution (bits) for a given PWM frequency: CCP1(2) Duty Cycle (1) Resolution (1) Note: Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as asserted high. 9.3.3 9.3.1 PWM PERIOD The PWM period is specified by writing to the PR2 register.
PIC16C745/765 TABLE 9-3: Address REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh, INTCON 10Bh,18Bh GIE PEIE T0IE INTE RBIE T0IF INTF RBIF Value on: POR, BOR Value on all other resets 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE
PIC16C745/765 10.0 UNIVERSAL SERIAL BUS 10.1.2 10.1 Overview Information communicated on the bus is grouped in a format called Frames. Each Frame is 1 ms in duration and is composed of multiple transfers. Each transfer type can be repeated more than once within a frame. This section introduces a minimum amount of information on USB. If you already have basic knowledge of USB, you can safely skip this section.
PIC16C745/765 The Device descriptor provides general information such as manufacturer, product number, serial number, USB device class the product falls under, and the number of different configurations supported. There can only be one Device descriptor for any given application. 10.2 The Configuration descriptor provides information on the power requirements of the device and how many different interfaces are supported when in this configuration.
PIC16C745/765 FIGURE 10-1: USB TOKENS USB RESET USB_RST Interrupt Generated SETUP TOKEN DATA ACK TOK_DNE Interrupt Generated IN TOKEN DATA ACK TOK_DNE Interrupt Generated OUT TOKEN DATA ACK TOK_DNE Interrupt Generated = Host = Device 1999-2013 Microchip Technology Inc.
PIC16C745/765 10.5 USB Register Map 10.5.1.1 The USB Control Registers, Buffer Descriptors and Buffers are located in Bank 3. 10.5.1 CONTROL AND STATUS REGISTERS The USB module is controlled by 7 registers, plus those that control each endpoint and endpoint/ direction buffer. USB Interrupt Register (UIR) The USB Interrupt Status Register (UIR) contains flag bits for each of the interrupt sources within the USB.
PIC16C745/765 10.5.1.2 USB Interrupt Enable Register (UIE) The USB Interrupt Enable Register (UIE) contains enable bits for each of the interrupt sources within the USB. Setting any of these bits will enable the respective interrupt source in the UIR register. The values in the UIE register only affect the propagation of an interrupt condition to the PIE1 register. Interrupt conditions can still be polled and serviced.
PIC16C745/765 10.5.1.3 USB Error Interrupt Status Register (UEIR) The USB Error Interrupt Status Register (UEIR) contains bits for each of the error sources within the USB. Each of these bits are enabled by their respective error enable bits (UEIE). The result is OR'ed together and sent to the ERROR bit of the UIR register. Once an interrupt bit has been set it must be cleared by writing a zero to the respective interrupt bit. Each bit is set as soon as the error condition is detected.
PIC16C745/765 10.5.1.4 Error Interrupt Enable Register (UEIE) The USB Error Interrupt Enable Register (UEIE) contains enable bits for each of the error interrupt sources within the USB. Setting any of these bits will enable the respective error interrupt source in the UEIR register.
PIC16C745/765 10.5.1.5 Status Register (USTAT) The USB Status Register reports the transaction status within the USB. When the MCU recognizes a TOK_DNE interrupt, this register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOK_DNE interrupt bit is asserted. The USTAT register is actually a read window into a status FIFO maintained by the USB. When the USB uses a BD, it updates the status register.
PIC16C745/765 10.5.1.6 USB Control Register (UCTRL) The control register provides various control and configuration information for the USB.
PIC16C745/765 10.5.1.7 USB Address Register (UADDR) The Address Register (UADDR) contains the unique USB address that the USB will decode. The register is reset to 00h after the RESET input has gone active or the USB has decoded a USB Reset signaling. That will initialize the address register to decode address 00h as required by the USB specification. The USB address must be written by the MCU during the USB SETUP phase.
PIC16C745/765 10.5.1.9 Endpoint Registers 10.5.1.10 USB Endpoint Control Register (EPCn) Each endpoint is controlled by an Endpoint Control Register. The PIC16C745/765 supports Buffer Descriptors (BD) for the following endpoints: - The Endpoint Control Register contains the endpoint control bits for each of the 6 endpoints available on USB for a decoded address. These four bits define the control necessary for any one endpoint.
PIC16C745/765 10.6 Buffer Descriptor Table (BDT) To efficiently manage USB endpoint communications the USB implements a Buffer Descriptor Table (BDT) in register space. Every endpoint requires a 4 byte Buffer Descriptor (BD) entry. Because the buffers are shared between the MCU and the USB, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and buffers in system memory. The UOWN bit is cleared when the BD entry is “owned” by the MCU.
PIC16C745/765 REGISTER 10-10: BUFFER DESCRIPTOR STATUS REGISTER. BITS WRITTEN BY THE MCU (BDndST: 1A0h, 1A4h, 1A8h, 1ACh, 1B0h, 1B4h) W-X UOWN bit7 W-X DATA0/1 U-X — U-X — W-X DTS W-X BSTALL U-X — U-X — bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset X = Don’t care bit 7: UOWN: USB Own This UOWN bit determines who currently owns the buffer. The SIE writes a 0 to this bit when it has completed a token.
PIC16C745/765 REGISTER 10-11: BUFFER DESCRIPTOR STATUS. BITS READ BY THE MCU (BDndST: 1A0h, 1A4h, 1A8h, 1ACh, 1B0h, 1B4h) R/W-0 UOWN bit7 R/W-X DATA0/1 R/W-X PID3 R/W-X PID2 R/W-X PID1 R/W-X PID0 U-X — U-X — bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset X = Don’t care bit 7: UOWN: USB Own This UOWN bit determines who currently owns the buffer. The SIE writes a 0 to this bit when it has completed a token.
PIC16C745/765 REGISTER 10-13: BUFFER DESCRIPTOR ADDRESS LOW (BDndAL: 1A2h, 1A6h, 1AAh, 1AEh, 1B2h, 1B6h) R/W-X BA7 bit7 R/W-X BA6 R/W-X BA5 R/W-X BA4 R/W-X BA3 R/W-X BA2 R/W-X BA1 R/W-X BA0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset X = Don’t care bit 7-0: BA<7:0>: Buffer Address The base address of the buffer controlled by this endpoint. The upper order bit address (BA8) of the 9-bit address is assumed to be 1h.
PIC16C745/765 10.9 USB Firmware Users Guide 10.9.3 10.9.1 INTRODUCING THE USB SOFTWARE INTERFACE 10.9.3.1 Microchip provides a layer of software that handles the lowest level interface so your application won’t have to. This provides a simple Put/Get interface for communication. Most of the USB processing takes place in the background through the Interrupt Service Routine. From the application viewpoint, the enumeration process and data communication takes place without further interaction.
PIC16C745/765 10.9.3.6 Buffer Allocation The PIC16C745/765 has 64 bytes of Dual Port RAM. 24 are used for the Buffer Descriptor Table (BDT), leaving 40 bytes for buffers. Endpoints 0 IN and OUT need dedicated buffers since a setup transaction can never be NAKed. That leaves three buffers for four possible Endpoints, but the USB spec requires that low speed devices are only allowed 2 endpoints (USB 1.1 paragraph 5.3.1.
PIC16C745/765 ConfiguredUSB (Macro) continuously polls the enumeration status bits and waits until the device has been configured by the host. This should be used after the call to InitUSB and prior to the first time your application attempts to communicate on the bus. SetConfiguration is a callback function that allows your application to associate some meaning to a Set Configuration command from the host.
PIC16C745/765 10.9.7 EXAMPLE This example shows how the USB functions are used. This example first initializes the USB peripheral, which allows the host to enumerate the device. The enumeration process occurs in the background, via an Interrupt Service Routine. This function waits until enumeration is complete, and then polls EP1 OUT to see if there is any data available. When a buffer is available, it is copied to the IN buffer.
PIC16C745/765 NOTES: DS41124D-page 76 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 11.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, Serial EEPROMs, etc. The USART can be configured in the following modes: The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI).
PIC16C745/765 REGISTER 11-2: RECEIVE STATUS AND CONTROL REGISTER (RCSTA: 18h) R/W-0 SPEN bit7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN U-0 — R-0 FERR R-0 OERR R-x RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception b
PIC16C745/765 11.1 USART Baud Rate Generator (BRG) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 11-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock).
PIC16C745/765 TABLE 11-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) 24 MHz Desired Baud Actual Baud % of Error SPBRG 300 1200 2400 4800 9600 9615.38 0.16 155 19200 19230.77 0.16 77 38400 38461.54 0.16 38 57600 57692.31 0.16 25 115200 115384.62 0.16 12 230400 250000.00 8.51 5 460800 500000.00 8.
PIC16C745/765 11.2 ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty.
PIC16C745/765 Steps to follow when setting up an Asynchronous Transmission: 4. 1. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 11.1) Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. 2. 3. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF.
PIC16C745/765 11.2.2 possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software.
PIC16C745/765 Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. 6. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 11.1). Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. TABLE 11-7: Address Name 0Ch PIR1 18h RCSTA 7. 8. 9.
PIC16C745/765 11.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner, i.e., transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16C745/765 TABLE 11-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 PSPIF(1) ADIF SPEN RX9 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 Bit 5 0Ch PIR1 18h RCSTA 19h TXREG USART Trans
PIC16C745/765 11.3.2 it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>).
PIC16C745/765 FIGURE 11-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRG = '0'. DS41124D-page 88 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 11.4 11.4.2 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode.
PIC16C745/765 TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 PSPIF(1) SPEN ADIF RCIF TXIF RX9 SREN CREN 0Ch PIR1 18h RCSTA 19h TXREG USART Transmit Register 8Ch PIE1 98h TXSTA 99h SPBRG Baud Rate Generator Register PSPIE(1) ADIE RCIE TXIE CSRC TX9 TXEN SYNC Bit 3 Bit 2 USBIF CCP1IF — FERR Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets TMR2IF TMR1IF 0000 0000 0000 0000 OERR RX9D 0000 -00x 0000
PIC16C745/765 12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has three registers. These registers are: The 8-bit Analog-To-Digital (A/D) converter module has five inputs for the PIC16C745 and eight for the PIC16C765. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital value. The output of the sample and hold is the input into the converter, which generates the result via successive approximation.
PIC16C745/765 REGISTER 12-1: A/D CONTROL REGISTER (ADCON0: 1Fh) R/W-0 R/W-0 ADCS1 ADCS0 bit7 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 — R/W-0 ADON bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR Reset bit 7-6: ADCS<1:0>: A/D Conversion Clock Select bits 00 = FINT/2 01 = FINT/8 10 = FINT/32(2) 11 = FRC (clock derived from dedicated internal oscillator)(2) bit 5-3: CHS<2:0>: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (R
PIC16C745/765 REGISTER 12-2: A/D CONTROL REGISTER 1 (ADCON1: 9Fh) U-0 — bit7 U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR Reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG<2:0>: A/D Port Configuration Control bits PCFG<2:0> AN7(1) 000 001 010 011 100 101 11x A A D D D A D AN6 A A D D D A D AN5 A A D D D A D AN4 A A A A D A D AN3 A VREF A VREF A VREF D AN2 A A A A D A D AN1 A A A
PIC16C745/765 The following steps should be followed for doing an A/D conversion: 4. 1. 5. 2. 3. Configure the A/D module: • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit Wait the required acquisition time.
PIC16C745/765 12.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), Figure 12-2.
PIC16C745/765 12.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • 2TOSC 8TOSC 32TOSC Dedicated Internal RC oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. TABLE 12-1: TAD vs.
PIC16C745/765 12.7 Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” of the CCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero.
PIC16C745/765 NOTES: DS41124D-page 98 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 13.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16C745/765 family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16C745/765 13.2 TABLE 13-1: Oscillator Configurations 13.2.1 OSCILLATOR TYPES The PIC16C745/765 can be operated in four different oscillator modes. The user can program a configuration bit (FOSC0) to select one of these four modes: • • • • EC E4 HS H4 External Clock External Clock with internal PLL enabled High Speed Crystal/Resonator High Speed Crystal/Resonator with internal PLL enabled Mode Freq OSC1 OSC2 HS 6.0 MHz 10 - 68 pF 10 - 68 pF These values are for design guidance only.
PIC16C745/765 13.2.5 EXTERNAL CLOCK IN 13.2.6 In EC mode, users may directly drive the PIC16C745/ 765 provided that this external clock source meets the AC/DC timing requirements listed in Section 17.4. Figure 13-2 below shows how an external clock circuit should be configured. E4 MODE In E4 mode, a PLL module is switched on in-line with the clock provided to OSC1. The output of the PLL drives FINT. Note: CLKOUT is the same frequency as OSC1 if in E4 mode, otherwise CLKOUT = OSC1/4.
PIC16C745/765 FIGURE 13-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT Time-out Module Reset VDD rise Power-on Reset detect VDD Brown-out Reset S OST/PWRT OST Chip Reset R 10-bit Ripple counter Q OSC1 PWRT Dedicated On-chip RC OSC 10-bit Ripple counter Enable PWRT Enable OST DS41124D-page 102 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 13.4 RESETS 13.4.4 13.4.1 POWER-ON RESET (POR) If VDD falls below VBOR (parameter D005) for longer than TBOR (parameter #35), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a RESET may not occur. A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD.
PIC16C745/765 13.
PIC16C745/765 TABLE 13-7: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA --0x 0000 --0u 0000 --uu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PORTC xx-- -xxx uu-- -uuu uu-- -uuu PORTD(4) xxxx xxxx uuuu uuuu u
PIC16C745/765 TABLE 13-7: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt TRISD(4) 1111 1111 1111 1111 uuuu uuuu TRISE(4) 0000 -111 0000 -111 uuuu -uuu PIE1 0000 0000 0000 0000 uuuu uuuu PIE2 ---- ---0 ---- ---0 ---- ---u ---- --uu ---- --uu Register PCON (3) ---- --0q PR2 1111 1111 1111 1111 1111 1111 TXSTA 0000 -010 0000 -010 uuuu -uuu SPBRG 0000 0000 0000 0000 uuuu uuuu ADCON1
PIC16C745/765 13.6 Interrupts Note: The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts or disables (if cleared) all interrupts.
PIC16C745/765 FIGURE 13-5: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC+2 Note 1: 2: 3: 4: PC + 2 PC+2 Instruction fetched Instruction executed Inst(PC + 2) Inst(PC + 1) Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) HS oscillator mode assumed. TOST = 1024TOSC (drawing not to scale).
PIC16C745/765 13.6.1 INT INTERRUPT 13.7 The external interrupt on RB0/INT pin is edge triggered: either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16C745/765 13.8 Watchdog Timer (WDT) ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Time-out periods up to 128 TWDT can be realized. The Watchdog Timer is a free running on-chip dedicated oscillator, which does not require any external components. The WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction.
PIC16C745/765 13.9 Other peripherals cannot generate interrupts, since during SLEEP, no on-chip Q clocks are present. Power-Down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the WDT will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16C745/765 FIGURE 13-8: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction fetched Instruction executed Note 1: 2: 3: 4: 13.10 PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) 13.
PIC16C745/765 14.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 14-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 14-1 shows the opcode field descriptions.
PIC16C745/765 TABLE 14-2: PIC16CXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move
PIC16C745/765 14.1 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [label] ADDLW Syntax: [label] ANDWF Operands: 0 k 255 Operands: 0 f 127 d k f,d Operation: (W) + k (W) Status Affected: C, DC, Z Operation: (W) .AND. (f) (destination) Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. Status Affected: Z Description: AND the W register with register 'f'.
PIC16C745/765 BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [label] BTFSS f,b Syntax: [label] CLRF Operands: 0 f 127 0b<7 Operands: 0 f 127 Operation: Operation: skip if (f) = 1 00h (f) 1Z Status Affected: None Status Affected: Z Description: If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction.
PIC16C745/765 COMF Complement f GOTO Unconditional Branch Syntax: [ label ] COMF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 2047 Operation: (f) (destination) Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. Description: GOTO is an unconditional branch.
PIC16C745/765 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: 0 k 255 Operation: (W) .OR. k (W) Operation: k (W) Status Affected: Z Status Affected: None Description: The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register. Description: The eight bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s.
PIC16C745/765 RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS PC, 1 GIE 0 f 127 d [0,1] Operation: See description below None Status Affected: C Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
PIC16C745/765 SUBLW Syntax: Subtract W from Literal [ label ] SUBLW k Operands: 0 k 255 Operands: 0 k 255 Operation: k - (W) W) Operation: (W) .XOR. k W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register. Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16C745/765 15.
PIC16C745/765 15.4 MPLINK/MPLIB Linker/Librarian MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with precompiled libraries using directives from a linker script. MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application.
PIC16C745/765 15.9 PRO MATE II Universal Programmer The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability.
PIC16C745/765 15.14 PICDEM-17 The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug and test the sample code.
1999-2013 Microchip Technology Inc. PRO MATE II Universal Programmer Preliminary PIC16F62X ** ** ** PIC16C7X † † * PIC16C7XX PIC16C8X PIC16F8XX PIC16C9XX PIC17C4X PIC17C7XX 125 kHz Anticollision microID Developer’s Kit 13.
PIC16C745/765 NOTES: DS41124D-page 126 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 16.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)........................................... -0.
PIC16C745/765 FIGURE 16-1: VALID OPERATING REGIONS, FREQUENCY ON FINT, -40°C TA +85°C 5.5 V Voltage 5.25 V 4.35 V 4.0 V 24 MHz Frequency DS41124D-page 128 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 16.1 DC Characteristics: PIC16C745/765 (Industrial) DC CHARACTERISTICS Param No. Sym Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Characteristic Min Typ† Max Units 4.35 — 5.25 V Conditions D001 VDD Supply Voltage D002* VDR RAM Data Retention Voltage (Note 1) — 1.
PIC16C745/765 16.2 DC Characteristics: PIC16C745/765 (Industrial) DC CHARACTERISTICS Param No.
PIC16C745/765 16.3 AC (Timing) Characteristics 16.3.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16C745/765 16.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 16-1 apply to all timing specifications unless otherwise noted. Figure 16-2 specifies the load conditions for the timing specifications. TABLE 16-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Operating voltage VDD range as described in DC spec Section 16.1 and Section 16.2.
PIC16C745/765 16.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 16-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT FIGURE 16-4: CLOCK MULTIPLIER (PLL) PHASE RELATIONSHIP OSC1/ CLKIN FINT Note 1: FINT represents the internal clock signal. FINT equals FOSC or CLKIN if the PLL is disabled. FINT equals 4x FOSC or 4x CLKIN if the PLL is enabled. TCY is always 4/FINT. FINT is OSC1 pin in EC mode, PLL disabled. 2: FINT = OSC1 in EC mode with PLL disabled.
PIC16C745/765 TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param No.
PIC16C745/765 FIGURE 16-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 FINT 11 10 CLKOUT 13 12 19 14 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 16-2 for load conditions. TABLE 16-3: Param No.
PIC16C745/765 FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 16-2 for load conditions. FIGURE 16-7: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Param No.
PIC16C745/765 FIGURE 16-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 16-2 for load conditions. TABLE 16-5: Param No. 40* TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Sym TT0H Characteristic T0CKI High Pulse Width No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler 42* TT0P T0CKI Period With Prescaler 46* TT1H TT1L T1CKI High Time T1CKI Low Time — — ns 10 — — ns 0.
PIC16C745/765 FIGURE 16-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure 16-2 for load conditions. TABLE 16-6: Param No. Sym 50* TCCL CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Characteristic CCP1 and CCP2 input low time No Prescaler With Prescaler 51* TCCH CCP1 and CCP2 input high time No Prescaler With Prescaler Min Typ† Max Units 0.5 TCY + 20 — — ns 10 — — ns 0.
PIC16C745/765 FIGURE 16-10: PARALLEL SLAVE PORT TIMING (PIC16C765) RE2/CS RE0/RD RE1/WR 65 RD<7:0> 62 64 63 Note: Refer to Figure 16-2 for load conditions. TABLE 16-7: Param No.
PIC16C745/765 FIGURE 16-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 16-2 for load conditions. TABLE 16-8: Param No.
PIC16C745/765 TABLE 16-10: A/D CONVERTER CHARACTERISTICS: PIC16C745/765 (INDUSTRIAL) Param No. Sym Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 8 bits bit A02 EABS Total Absolute error — — <±1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.
PIC16C745/765 FIGURE 16-13: A/D CONVERSION TIMING 1 TCY BSF ADCON0, GO 134 (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Note: TABLE 16-11: A/D CONVERSION REQUIREMENTS Param No. 130 Sym TAD Characteristic A/D clock period Min Typ† Max Units Conditions 1.
PIC16C745/765 FIGURE 16-14: MAXIMUM INPUT WAVEFORM TIMING SPECIFICATIONS 66.7ns 6MHz RSRC Pin V 60ns min 4.6V -1.0V RSRC = 39 ± 2% 4ns min 20ns max 4ns min 20ns max Note 1: The D+/D- signals can withstand a continuous short to VBUS, GND, cable shield or any other signal. FIGURE 16-15: USB LOW SPEED SIGNALING Data Differential Lines 90% 90% 72 10% 10% 71 70 Note 1: Parameters are per USB Specification 1.1.
PIC16C745/765 NOTES: DS41124D-page 144 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 17.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range. This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time.
PIC16C745/765 FIGURE 17-3: DC LOAD LINES FOR USB REGULATOR OUTPUT (VUSB) 3 2 -4 85 °C 1 0° C 25 °C Regulation Voltage (V) 4 0 0 5 10 15 20 25 30 35 40 45 -1 -2 Load Current (mA) DS41124D-page 146 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 18.0 PACKAGING INFORMATION 18.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example PIC16C745-I/SP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 9917017 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC16C745-I/SO 9917017 Example 28-Lead Side Braze Windowed (JW) XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC16C745/765 Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN PIC16C765-I/P 9917017 44-Lead TQFP Example PIC16C765-I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 9917017 44-Lead PLCC Example PIC16C765-I/L XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 9917017 40-Lead CERDIP Windowed Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS41124D-page 148 Preliminary PIC16C745-I/JW 9905017 1999-2013 Microchip Technology
PIC16C745/765 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 2.54 .100 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 8.
PIC16C745/765 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C745/765 28-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C745/765 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 1 n E A2 A L c B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.
PIC16C745/765 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D 2 1 n E A2 L c B1 B eB Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC16C745/765 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C745/765 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3 A2 35 A B1 B c E2 Units Dimension Limits n p A1 p D2 INCHES* NOM 44 .050 11 .165 .173 .145 .153 .028 .020 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .
PIC16C745/765 NOTES: DS41124D-page 156 Preliminary 1999-2013 Microchip Technology Inc.
PIC16C745/765 INDEX A C A/D ADCON0 Register ..................................................... 91 Analog Input Model Block Diagram ........................... 95 Analog-to-Digital Converter ....................................... 91 Block Diagram ........................................................... 94 Configuring Analog Port Pins .................................... 96 Configuring the Interrupt ............................................ 94 Configuring the Module ...............................
PIC16C745/765 I L I/O Ports ............................................................................ 31 PORTA ...................................................................... 31 PORTB ...................................................................... 33 PORTC ...................................................................... 35 PORTD ............................................................... 37, 40 PORTE ......................................................................
PIC16C745/765 Power-on Reset (POR) Timing Diagram ....................................................... 136 PR2 Register .............................................................. 18, 49 PRO MATE II Universal Programmer ........................... 123 Product Identification System .......................................... 163 Program Counter PCLATH Register .................................................... 109 Program Memory Paging .................................................................
PIC16C745/765 USART Synchronous Transmission (Master/Slave) ......................................................... 140 Watchdog Timer (WDT) ........................................... 136 TMR0 ................................................................................. 20 TMR0 Register .................................................................. 17 TMR1CS bit ....................................................................... 45 TMR1H .......................................................
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PIC16C745/765 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PIC16C745/765 DS41124D-page 164 Preliminary 1999-2013 Microchip Technology Inc.
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