Datasheet

 1997 Microchip Technology Inc. DS30390E-page 281
PIC16C7X
Figure 12-5: RX Pin Sampling Scheme, BRGH = 1
(PIC16C73/73A/74/74A) ......................... 104
Figure 12-6: RX Pin Sampling Scheme,
BRGH = 0 OR BRGH = 1 (
PIC16C76/77) ......................................... 105
Figure 12-7: USART Transmit Block Diagram............. 106
Figure 12-8: Asynchronous Master Transmission....... 107
Figure 12-9: Asynchronous Master Transmission
(Back to Back)......................................... 107
Figure 12-10: USART Receive Block Diagram.............. 108
Figure 12-11: Asynchronous Reception ........................ 108
Figure 12-12: Synchronous Transmission..................... 111
Figure 12-13: Synchronous Transmission
(Through TXEN)...................................... 111
Figure 12-14: Synchronous Reception
(Master Mode, SREN)............................. 113
Figure 13-1: ADCON0 Register (Address 1Fh)........... 117
Figure 13-2: ADCON1 Register (Address 9Fh)........... 118
Figure 13-3: A/D Block Diagram.................................. 119
Figure 13-4: Analog Input Model ................................. 120
Figure 13-5: A/D Transfer Function............................. 125
Figure 13-6: Flowchart of A/D Operation..................... 126
Figure 14-1: Configuration Word for
PIC16C73/74........................................... 129
Figure 14-2: Configuration Word for
PIC16C72/73A/74A/76/77....................... 130
Figure 14-3: Crystal/Ceramic Resonator
Operation (HS, XT or LP
OSC Configuration)................................. 131
Figure 14-4: External Clock Input Operation
(HS, XT or LP OSC Configuration) ......... 131
Figure 14-5: External Parallel Resonant Crystal
Oscillator Circuit...................................... 132
Figure 14-6: External Series Resonant Crystal
Oscillator Circuit..................................... 132
Figure 14-7: RC Oscillator Mode................................. 132
Figure 14-8: Simplified Block Diagram of On-chip
Reset Circuit............................................ 133
Figure 14-9: Brown-out Situations............................... 134
Figure 14-10: Time-out Sequence on Power-up
(MCLR
not Tied to VDD): Case 1............. 139
Figure 14-11: Time-out Sequence on Power-up
(MCLR Not Tied To VDD): Case 2.......... 139
Figure 14-12: Time-out Sequence on Power-up
(MCLR Tied to VDD)................................ 139
Figure 14-13: External Power-on Reset Circuit
(for Slow VDD Power-up)......................... 140
Figure 14-14: External Brown-out Protection
Circuit 1................................................... 140
Figure 14-15: External Brown-out Protection
Circuit 2................................................... 140
Figure 14-16: Interrupt Logic ......................................... 142
Figure 14-17: INT Pin Interrupt Timing.......................... 142
Figure 14-18: Watchdog Timer Block Diagram ............. 144
Figure 14-19: Summary of Watchdog
Timer Registers....................................... 144
Figure 14-20: Wake-up from Sleep Through
Interrupt................................................... 146
Figure 14-21: Typical In-Circuit Serial
Programming Connection ....................... 146
Figure 15-1: General Format for Instructions .............. 147
Figure 17-1: Load Conditions ...................................... 172
Figure 17-2: External Clock Timing ............................. 173
Figure 17-3: CLKOUT and I/O Timing......................... 174
Figure 17-4: Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing......................................................175
Figure 17-5: Brown-out Reset Timing ..........................175
Figure 17-6: Timer0 and Timer1 External
Clock Timings .........................................176
Figure 17-7: Capture/Compare/PWM
Timings (CCP1) .......................................177
Figure 17-8: SPI Mode Timing .....................................178
Figure 17-9: I
2
C Bus Start/Stop Bits Timing.................179
Figure 17-10: I
2
C Bus Data Timing................................180
Figure 17-11: A/D Conversion Timing............................182
Figure 18-1: Load Conditions.......................................188
Figure 18-2: External Clock Timing..............................189
Figure 18-3: CLKOUT and I/O Timing..........................190
Figure 18-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and Power-up Tim-
er Timing..................................................191
Figure 18-5: Timer0 and Timer1 External
Clock Timings .........................................192
Figure 18-6: Capture/Compare/PWM Timings
(CCP1 and CCP2) ...................................193
Figure 18-7: Parallel Slave Port Timing
(PIC16C74)..............................................194
Figure 18-8: SPI Mode Timing .....................................195
Figure 18-9: I
2
C Bus Start/Stop Bits Timing.................196
Figure 18-10: I
2
C Bus Data Timing................................197
Figure 18-11: USART Synchronous Transmission
(Master/Slave) Timing..............................198
Figure 18-12: USART Synchronous Receive
(Master/Slave) Timing..............................198
Figure 18-13: A/D Conversion Timing............................200
Figure 19-1: Load Conditions.......................................206
Figure 19-2: External Clock Timing..............................207
Figure 19-3: CLKOUT and I/O Timing..........................208
Figure 19-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Timing ...........................209
Figure 19-5: Brown-out Reset Timing ..........................209
Figure 19-6: Timer0 and Timer1 External
Clock Timings .........................................210
Figure 19-7: Capture/Compare/PWM Timings
(CCP1 and CCP2) ...................................211
Figure 19-8: Parallel Slave Port Timing
(PIC16C74A) ...........................................212
Figure 19-9: SPI Mode Timing .....................................213
Figure 19-10: I
2
C Bus Start/Stop Bits Timing.................214
Figure 19-11: I
2
C Bus Data Timing................................215
Figure 19-12: USART Synchronous Transmission
(Master/Slave) Timing..............................216
Figure 19-13: USART Synchronous Receive
(Master/Slave) Timing..............................216
Figure 19-14: A/D Conversion Timing............................218
Figure 20-1: Load Conditions.......................................225
Figure 20-2: External Clock Timing..............................226
Figure 20-3: CLKOUT and I/O Timing..........................227
Figure 20-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Timing ...........................228
Figure 20-5: Brown-out Reset Timing ..........................228
Figure 20-6: Timer0 and Timer1 External
Clock Timings ..........................................229
Figure 20-7: Capture/Compare/PWM Timings
(CCP1 and CCP2) ...................................230
Figure 20-8: Parallel Slave Port Timing
(PIC16C77).............................................231