Datasheet

PIC16C7X
DS30390E-page 182  1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-11: A/D CONVERSION TIMING
TABLE 17-11: A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
130 T
AD A/D clock period PIC16C72 1.6 — — µsTOSC based, VREF ≥ 3.0V
PIC16LC72 2.0 — — µsTOSC based, VREF full range
PIC16C72 2.0 4.0 6.0 µs A/D RC Mode
PIC16LC72 3.0 6.0 9.0 µs A/D RC Mode
131 TCNV Conversion time (not including S/H
time) (Note 1)
— 9.5 — TAD
132 TACQ Acquisition time Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135 TSWC Switching from convert → sample time 1.5 § — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(T
OSC/2)
(1)
7 6 5432 10
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
134