Datasheet

 1997 Microchip Technology Inc. DS30390E-page 143
PIC16C7X
14.5.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 14.8 for details on SLEEP mode.
14.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 7.0)
14.5.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note: For the PIC16C73/74, if a change on the
I/O pin should occur when the read opera-
tion is being executed (start of the Q2
cycle), then the RBIF interrupt flag may not
get set.
14.6 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
Example 14-1 stores and restores the STATUS, W, and
PCLATH registers. The register, W_TEMP, must be
defined in each bank and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the ISR code.
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
Applicable Devices
72
73 73A 74 74A 76 77
EXAMPLE 14-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
BCF STATUS, IRP ;Return to Bank 0
MOVF FSR, W ;Copy FSR to W
MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP
:
:(ISR)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W