Information

2001 Microchip Technology Inc. DS80088A-page 1
PIC16C73A
The PIC16C73A (Rev. A) parts you have received con-
form functionally to the Device Data Sheet
(DS30390E), except for the anomalies described
below.
All the problems listed here will be addressed in future
revisions of the PIC16C73A silicon.
1. Module: 8-bit A/D Module
If the Analog Port is configured so that all analog
pins are digital inputs (PCFG2:PCFG0 = 11x),
then doing a conversion on any pin of the analog
port will give a result of ADRES = 0xFF.
Work around
Configure the PCFG2:PCFG0 bits to a value that
has any pin of the analog port configured as an
analog input (such as PCFG2:PCFG0 = 100).
Conversion on any pin of the analog port (analog
or digital) will now convert as expected.
2. Module: CCP (Compare Mode)
The Compare mode may not operate as expected
when configuring the compare match to drive the
I/O pin low (CCPxM<3:0> = 1001).
When the CCP module is changed to compare
output low (CCPxM<3:0> = 1001) from any other
non-compare CCP mode, the I/O pin will immedi-
ately be driven low, regardless of the state of the
I/O data latch. The pin will remain low when the
compare match occurs (see Table 1).
However, when the CCP module is changed to
compare output high (CCPxM<3:0> = 1000) from
any other CCP mode, the I/O pin will immediately
be driven low, regardless of the state of the I/O
data latch. The pin will be driven high when the
compare match occurs.
TABLE 1: COMPARE OUTPUT LOW
SWITCHING
Work around
To have the I/O pin high until the compare match
low occurs, force a compare match high to get the
I/O pin into the high state, then reconfigure the
compare match to force the I/O low when the com-
pare condition occurs.
CCP Mode
CCPxM<3:0> =
I/O pin
State
Change CCP to
CCPxM<3:0> =
1001 1000
0xxx
HLL
LLL
1000
HH
LL
1001
H—L
L—L
101x
HLL
LLL
11xx
HLL
LLL
PIC16C73A Rev. A Silicon Errata Sheet

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