Datasheet
PIC16C7X
DS30390E-page 68 1997 Microchip Technology Inc.
8.5 Resetting Timer1 using a CCP Trigger
Output
The CCP2 module is not implemented on the
PIC16C72 device.
If the CCP1 or CCP2 module is configured in compare
mode to generate a “special event trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
Applicable Devices
72
73 73A 74 74A 76 77
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
8.6 Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 and CCP2
special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
8.7 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Applicable Devices
72
73 73A 74 74A 76 77
Applicable Devices
72
73 73A 74 74A 76 77
TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
0000 000x 0000 000u
0Ch PIR1 PSPIF
(1,2)
ADIF RCIF
(2)
TXIF
(2)
SSPIF CCP1IF TMR2IF TMR1IF
0000 0000 0000 0000
8Ch PIE1 PSPIE
(1,2)
ADIE RCIE
(2)
TXIE
(2)
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.