Datasheet

PIC16C7X

DS30390E-page 38  1997 Microchip Technology Inc.

4.2.2.7 PIR2 REGISTER

This register contains the CCP2 interrupt ﬂag bit.

Applicable Devices

72 73 73A 74 74A 76 77

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt ﬂag bits are clear prior to enabling an

interrupt.

FIGURE 4-15: PIR2 REGISTER (ADDRESS 0Dh)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IF R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-1: Unimplemented: Read as '0'

bit 0: CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused

Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to

enabling an interrupt.