Datasheet

PIC16C7X

DS30390E-page 264  1997 Microchip Technology Inc.

APPENDIX C: WHAT’S NEW

Added the following devices:

• PIC16C76

• PIC16C77

Removed the PIC16C710, PIC16C71, PIC16C711

from this datasheet.

Added PIC16C76 and PIC16C77 devices. The

PIC16C76/77 devices have 368 bytes of data memory

distributed in 4 banks and 8K of program memory in 4

pages. These two devices have an enhanced SPI that

supports both clock phase and polarity. The USART

has been enhanced.

When upgrading to the PIC16C76/77 please note that

the upper 16 bytes of data memory in banks 1,2, and 3

are mapped into bank 0. This may require relocation of

data memory usage in the user application code.

Added Q-cycle deﬁnitions to the Instruction Set Sum-

mary section.

APPENDIX D: WHAT’S CHANGED

Minor changes, spelling and grammatical changes.

Added the following note to the USART section. This

note applies to all devices except the PIC16C76 and

PIC16C77.

For the PIC16C73/73A/74/74A the asynchronous high

speed mode (BRGH = 1) may experience a high rate of

receive errors. It is recommended that BRGH = 0. If you

desire a higher baud rate than BRGH = 0 can support,

refer to the device errata for additional information or

use the PIC16C76/77.

Divided SPI section into SPI for the PIC16C76/77 and

SPI for all other devices.