PIC16C7X 8-Bit CMOS Microcontrollers with A/D Converter • Wide operating voltage range: 2.5V to 6.
PIC16C7X Pin Diagrams SDIP, SOIC, Windowed Side Brazed Ceramic SSOP •1 28 RB7 MCLR/VPP •1 28 RB7 RA0/AN0 2 27 RB6 RA0/AN0 2 27 RB6 RA1/AN1 3 26 RB5 RA1/AN1 3 26 RB5 RA2/AN2 4 25 RB4 RA2/AN2 4 25 RB4 RA3/AN3/VREF 5 24 RB3 RA3/AN3/VREF 5 24 RB3 RA4/T0CKI 6 23 RB2 RA4/T0CKI 6 23 RB2 RA5/SS/AN4 VSS 7 8 22 21 RB1 RB0/INT RA5/SS/AN4 VSS 7 8 22 21 RB1 RB0/INT OSC1/CLKIN MCLR/VPP 9 20 VDD OSC1/CLKIN 9 20 VDD OSC2/CLKOUT 10 19 VSS OSC2/CLKOUT 10
PIC16C7X 1 2 3 4 5 6 7 8 9 10 11 PIC16C74 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/SS/AN4 RA4/T0CKI MQFP TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 PIC16C74A PIC16C77 12 13 14 15 16 17 18 19 20 21 22 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF PIC16C74 PIC16C74A P
PIC16C7X Table of Contents 1.0 General Description ....................................................................................................................................................................... 5 2.0 PIC16C7X Device Varieties ........................................................................................................................................................... 7 3.0 Architectural Overview ............................................................................
PIC16C7X 1.0 GENERAL DESCRIPTION The PIC16C7X is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC16C7X TABLE 1-1: PIC16C7XX FAMILY OF DEVCES PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72(1) Maximum Frequency of Operation (MHz) 20 20 20 20 20 20 EPROM Program Memory (x14 words) 512 1K 1K 2K 2K — ROM Program Memory (14K words) — — — — — 2K Data Memory (bytes) 36 36 68 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/ Peripherals PWM Module(s) — — — — 1 1 Serial Port(s) (SPI/I2C, USART) — —
PIC16C7X 2.0 PIC16C7X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C7X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C7X family, there are two device “types” as indicated in the device number: 1. 2. 2.
PIC16C7X NOTES: DS30390E-page 8 1997 Microchip Technology Inc.
PIC16C7X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus.
PIC16C7X FIGURE 3-1: PIC16C72 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 RAM File Registers 128 x 8 8 Level Stack (13-bit) 2K x 14 8 Data Bus Program Counter EPROM RAM Addr(1) PORTB 9 Addr MUX Instruction reg 7 Direct Addr 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation ALU MCLR RC0/T1OSO/T1CKI RC1/T1OS
PIC16C7X FIGURE 3-2: Device PIC16C73/73A/76 BLOCK DIAGRAM Program Memory Data Memory (RAM) PIC16C73 PIC16C73A PIC16C76 4K x 14 4K x 14 8K x 14 192 x 8 192 x 8 368 x 8 13 8 Data Bus Program Counter PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 EPROM Program Memory Program Bus RAM File Registers 8 Level Stack (13-bit) 14 RAM Addr(1) PORTB 9 Addr MUX Instruction reg 7 Direct Addr 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 MUX Power-up Timer Instruction
PIC16C7X FIGURE 3-3: Device PIC16C74/74A/77 BLOCK DIAGRAM Program Memory Data Memory (RAM) PIC16C74 PIC16C74A PIC16C77 4K x 14 4K x 14 8K x 14 192 x 8 192 x 8 368 x 8 13 8 Data Bus Program Counter PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 EPROM Program Memory Program Bus RAM File Registers 8 Level Stack (13-bit) 14 RAM Addr (1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 Power-up Timer Instruction Dec
PIC16C7X TABLE 3-1: PIC16C72 PINOUT DESCRIPTION DIP Pin# SSOP Pin# SOIC Pin# I/O/P Type OSC1/CLKIN 9 9 9 I OSC2/CLKOUT 10 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PIC16C7X TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION DIP Pin# SOIC Pin# I/O/P Type OSC1/CLKIN 9 9 I OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PIC16C7X TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION DIP Pin# PLCC Pin# QFP Pin# I/O/P Type OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device.
PIC16C7X TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.’d) Pin Name DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output.
PIC16C7X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-4.
PIC16C7X NOTES: DS30390E-page 18 1997 Microchip Technology Inc.
PIC16C7X 4.0 MEMORY ORGANIZATION FIGURE 4-2: Applicable Devices 72 73 73A 74 74A 76 77 Program Memory Organization The PIC16C7X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space.
PIC16C7X FIGURE 4-3: PIC16C76/77 PROGRAM MEMORY MAP AND STACK 4.2 Applicable Devices 72 73 73A 74 74A 76 77 PC<12:0> CALL, RETURN RETFIE, RETLW The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.
PIC16C7X FIGURE 4-4: PIC16C72 REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIR1 PCLATH INTCON PIE1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON PCON ADRES ADCON0 General Purpose Register PR2 SSPADD SSPSTAT ADCON1 General Purpose Register FIGURE 4-5: Fil
PIC16C7X FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) PORTE (1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register Indirect addr.
PIC16C7X 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. TABLE 4-1: Address Name The special function registers can be classified into two sets (core and peripheral).
PIC16C7X TABLE 4-1: Address Name PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C7X TABLE 4-2: Address Name PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 (4) 03h STATUS 04h(4) FSR 05h PORT
PIC16C7X TABLE 4-2: Address Name PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C7X TABLE 4-3: Address PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 (4) 03h STATUS 04h(4) FSR 05h PORTA 06h
PIC16C7X TABLE 4-3: Address PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C7X TABLE 4-3: Address PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C7X 4.2.2.1 STATUS REGISTER Applicable Devices 72 73 73A 74 74A 76 77 For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register.
PIC16C7X 4.2.2.2 OPTION REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-8: R/W-1 RBPU bit7 To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16C7X 4.2.2.3 INTCON REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 4-9: R/W-0 GIE bit7 Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16C7X 4.2.2.4 PIE1 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts.
PIC16C7X FIGURE 4-11: PIE1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 8Ch) R/W-0 PSPIE(1) bit7 R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART re
PIC16C7X 4.2.2.5 PIR1 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: This register contains the individual flag bits for the Peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C7X FIGURE 4-13: PIR1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 0Ch) R/W-0 PSPIF(1) bit7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6: ADIF: A/D Converter Interrupt Flag bit
PIC16C7X 4.2.2.6 PIE2 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 This register contains the individual enable bit for the CCP2 peripheral interrupt.
PIC16C7X 4.2.2.7 PIR2 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 . Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. U-0 — R/W-0 CCP2IF bit0 This register contains the CCP2 interrupt flag bit.
PIC16C7X 4.2.2.8 PCON REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. BOR is unknown on Power-on Reset.
PIC16C7X 4.3 PCL and PCLATH Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. Applicable Devices 72 73 73A 74 74A 76 77 The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-17 shows the two situations for the loading of the PC.
PIC16C7X Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used). 4.5 EXAMPLE 4-1: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.
PIC16C7X NOTES: DS30390E-page 42 1997 Microchip Technology Inc.
PIC16C7X 5.0 I/O PORTS FIGURE 5-1: Applicable Devices 72 73 73A 74 74A 76 77 Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 Data bus BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS D Q VDD WR Port Q CK PORTA and TRISA Registers Data Latch Applicable Devices 72 73 73A 74 74A 76 77 D WR TRIS PORTA is a 6-bit latch.
PIC16C7X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST Function Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input or VREF Input/output or external clock input for Timer0 Output is open drain type RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input Legend: TTL = TTL input, ST = Schmitt Trigger input
PIC16C7X 5.2 PORTB and TRISB Registers Applicable Devices 72 73 73A 74 74A 76 77 PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).
PIC16C7X FIGURE 5-4: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C73/74) FIGURE 5-5: VDD RBPU(2) weak P pull-up Data Latch D Q Data bus WR Port I/O pin(1) CK WR TRIS VDD RBPU(2) Data bus WR Port TRIS Latch D Q TTL Input Buffer CK RD TRIS Q BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C72/ 73A/74A/76/77) weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q ST Buffer WR TRIS Latch D TTL Input Buffer CK RD TRIS Q ST Buffer Latch D EN RD Port Set RBIF EN RD Port Q1 Set RBIF From other RB7:RB4
PIC16C7X TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB 1111 1111 1111 1111 81h, 181h OPTION 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C7X 5.3 PORTC and TRISC Registers FIGURE 5-6: Applicable Devices 72 73 73A 74 74A 76 77 PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin.
PIC16C7X TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC 1111 1111 1111 1111 PORTC Data Direction Register Legend: x = unknown, u = unchanged. 1997 Microchip Technology Inc.
PIC16C7X 5.4 PORTD and TRISD Registers FIGURE 5-7: Applicable Devices 72 73 73A 74 74A 76 77 Data bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. D WR PORT PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PIC16C7X 5.5 PORTE and TRISE Register Note: Applicable Devices 72 73 73A 74 74A 76 77 On a Power-on Reset these pins are configured as analog inputs. FIGURE 5-8: PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. Data bus D WR PORT I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set.
PIC16C7X TABLE 5-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode or analog input: WR 1 = Not a write operation 0 = Write operation.
PIC16C7X 5.6 I/O Programming Considerations EXAMPLE 5-4: Applicable Devices 72 73 73A 74 74A 76 77 5.6.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC16C7X 5.7 Parallel Slave Port Applicable Devices 72 73 73A 74 74A 76 77 PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input pin RE0/RD/AN5 and WR control input pin RE1/WR/AN6. It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch.
PIC16C7X FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Address Name Bit 7 Bit 6 08h PORTD 09h PORTE — — 89h TRISE IBF OBF Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port data latch when written: Port pins when read — — IB
PIC16C7X NOTES: DS30390E-page 56 1997 Microchip Technology Inc.
PIC16C7X 6.0 OVERVIEW OF TIMER MODULES Applicable Devices 72 73 73A 74 74A 76 77 CCP module, Timer1 is the time-base for 16-bit Capture or the 16-bit Compare and must be synchronized to the device. 6.3 Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C72, PIC16C73/73A, PIC16C74/74A, PIC16C76/77 each have three timer modules. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer overflow). Each of these modules is explained in full detail in the following sections.
PIC16C7X NOTES: DS30390E-page 58 1997 Microchip Technology Inc.
PIC16C7X 7.0 TIMER0 MODULE Source Edge Select bit T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. Applicable Devices 72 73 73A 74 74A 76 77 The Timer0 module timer/counter has the following features: • • • • • • The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>).
PIC16C7X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0,W PC+3 Instruction Execute PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 PC+6 NT0+1 NT0 Write TMR0 executed FIGURE 7-4: PC+4 MOVF TMR0,W T0+1 T0 TMR0 PC+2 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 rea
PIC16C7X 7.2 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value.
PIC16C7X 7.3 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. Applicable Devices 72 73 73A 74 74A 76 77 When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
PIC16C7X 7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
PIC16C7X NOTES: DS30390E-page 64 1997 Microchip Technology Inc.
PIC16C7X 8.0 TIMER1 MODULE In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Applicable Devices 72 73 73A 74 74A 76 77 The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h.
PIC16C7X 8.1 Timer1 Operation in Timer Mode 8.2.1 Applicable Devices 72 73 73A 74 74A 76 77 When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TMR1 after synchronization. Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4.
PIC16C7X 8.3 Timer1 Operation in Asynchronous Counter Mode Applicable Devices 72 73 73A 74 74A 76 77 If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 8.3.2).
PIC16C7X 8.5 Resetting Timer1 using a CCP Trigger Output 8.6 Applicable Devices 72 73 73A 74 74A 76 77 Applicable Devices 72 73 73A 74 74A 76 77 The CCP2 module is not implemented on the PIC16C72 device. If the CCP1 or CCP2 module is configured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1.
PIC16C7X 9.0 TIMER2 MODULE 9.1 Applicable Devices 72 73 73A 74 74A 76 77 Applicable Devices 72 73 73A 74 74A 76 77 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register PR2.
PIC16C7X FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — bit7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit0 bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescal
PIC16C7X 10.0 CAPTURE/COMPARE/PWM MODULE(s) Applicable Devices 72 73 73A 74 74A 76 77 CCP1 72 73 73A 74 74A 76 77 CCP2 Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Both the CCP1 and CCP2 modules are identical in operation, with the exception of the operation of the special event trigger.
PIC16C7X FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh) U-0 — bit7 U-0 — R/W-0 CCPxX R/W-0 R/W-0 CCPxY CCPxM3 R/W-0 CCPxM2 R/W-0 R/W-0 CCPxM1 CCPxM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
PIC16C7X 10.1.4 CCP PRESCALER 10.2.1 There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler.
PIC16C7X 10.3 PWM Mode 10.3.1 Applicable Devices 72 73 73A 74 74A 76 77 In Pulse Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.
PIC16C7X EXAMPLE 10-2: PWM PERIOD AND DUTY CYCLE CALCULATION In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. Desired PWM frequency is 78.125 kHz, Fosc = 20 MHz TMR2 prescale = 1 Table 10-3 lists example PWM frequencies and resolutions for Fosc = 20 MHz. The TMR2 prescaler and PR2 values are also shown. 1/78.125 kHz= [(PR2) + 1] • 4 • 1/20 MHz • 1 12.8 µs = [(PR2) + 1] • 4 • 50 ns • 1 10.3.
PIC16C7X TABLE 10-5: Address REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name 0Bh,8Bh, INTCON 10Bh,18Bh 0Ch PIR1 Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh(2) PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1
Applicable Devices 72 73 73A 74 74A 76 77 11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 11.1 SSP Module Overview PIC16C7X The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
Applicable Devices PIC16C7X 11.2 72 73 73A 74 74A 76 77 SPI Mode for PIC16C72/73/73A/74/74A This section contains register definitions and operational characteristics of the SPI module for the PIC16C72, PIC16C73, PIC16C73A, PIC16C74, PIC16C74A.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 WCOL bit7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSP
PIC16C7X 11.2.1 Applicable Devices 72 73 73A 74 74A 76 77 OPERATION OF SSP MODULE IN SPI MODE Applicable Devices 72 73 73A 74 74A 76 77 The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear enable bit SSPEN, re-initialize SSPCON register, and then set enable bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 point at which it was taken high. External pull-up/ pull-down resistors may be desirable, depending on the application. The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set the for synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.3 SPI Mode for PIC16C76/77 This section contains register definitions and operational characteristics of the SPI module on the PIC16C76 and PIC16C77 only.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C76/77) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = N
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.3.1 SPI MODE FOR PIC16C76/77 The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-13: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C76/77) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit3 bit4 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 11-2: Address REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C76/77) Name Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF PIR1 PSPIF(1) ADIF
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 I 2C™ Overview 11.4 This section provides an overview of the Inter-Integrated Circuit (I 2C) bus, with Section 11.5 discussing the operation of the SSP module in I2C mode. The I 2C bus is a two-wire serial interface developed by the Philips Corporation. The original specification, or standard mode, was for data transfers of up to 100 Kbps. The enhanced specification (fast mode) is also supported.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 ADDRESSING I 2C DEVICES 11.4.2 FIGURE 11-17: SLAVE-RECEIVER ACKNOWLEDGE There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure 11-15). The more complex is the 10-bit address with a R/W bit (Figure 11-16). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this to be a 10-bit address.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 SCL is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 11-21. Figure 11-19 and Figure 11-20 show Master-transmitter and Master-receiver data transfer sequences.
Applicable Devices PIC16C7X 11.4.4 72 73 73A 74 74A 76 77 MULTI-MASTER 11.2.4.2 Clock Synchronization The I2C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur. 11.4.4.1 ARBITRATION Arbitration takes place on the SDA line, while the SCL line is high.
Applicable Devices 72 73 73A 74 74A 76 77 11.5 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer.
Applicable Devices PIC16C7X 11.5.1 72 73 73A 74 74A 76 77 SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.5.1.2 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
Applicable Devices PIC16C7X 11.5.1.3 72 73 73A 74 74A 76 77 TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>).
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.5.2 11.5.3 MASTER MODE In multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions.
Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-27: OPERATION OF THE I 2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR → SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Se
PIC16C7X 12.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.
PIC16C7X FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 SPEN bit7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN U-0 — R-0 FERR R-0 OERR R-x RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception b
PIC16C7X 12.1 USART Baud Rate Generator (BRG) EXAMPLE 12-1: CALCULATING BAUD RATE ERROR Applicable Devices 72 73 73A 74 74A 76 77 Desired Baud rate = Fosc / (64 (X + 1)) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored.
PIC16C7X TABLE 12-3: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz KBAUD NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53 16 MHz SPBRG value % KBAUD ERROR (decimal) +1.73 +0.16 +0.16 -1.96 0 - 255 64 51 16 9 0 255 FOSC = 5.0688 MHz BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW +0.16 +0.16 -0.79 +2.56 0 - 207 51 41 12 7 0 255 4 MHz NA NA NA 9.766 19.23 75.76 96.15 312.
PIC16C7X TABLE 12-5: BAUD RATE (K) 9.6 19.2 38.4 57.6 115.2 250 625 1250 BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz KBAUD 9.615 19.230 37.878 56.818 113.636 250 625 1250 16 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 -1.36 -1.36 -1.36 0 0 0 129 64 32 21 10 4 1 0 9.615 19.230 38.461 58.823 111.111 250 NA NA 10 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 +0.16 +2.12 -3.55 0 - 103 51 25 16 8 3 - 9.615 18.939 39.062 56.818 125 NA 625 NA 7.
PIC16C7X 12.1.1 set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge after the first falling edge of a x4 clock (Figure 12-4 and Figure 12-5). SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. If bit BRGH (TXSTA<2>) is clear (i.e.
PIC16C7X FIGURE 12-6: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 (PIC16C76/77) Start bit RX (RC7/RX/DT pin) Bit0 Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples 1997 Microchip Technology Inc.
PIC16C7X 12.2 USART Asynchronous Mode flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register.
PIC16C7X Steps to follow when setting up an Asynchronous Transmission: 4. 1. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 12.1) Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. 2. 3. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF.
PIC16C7X 12.2.2 double buffered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full then overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software.
PIC16C7X 6. Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 12.1). Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. TABLE 12-7: Address Name 7. 8. 9.
PIC16C7X 12.3 USART Synchronous Master Mode Applicable Devices 72 73 73A 74 74A 76 77 In Synchronous Master mode, the data is transmitted in a half-duplex manner i.e. transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines respectively.
PIC16C7X TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 18h RCSTA SPEN RX9 SREN CREN — FERR OERR 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 000
PIC16C7X 12.3.2 Steps to follow when setting up a Synchronous Master Reception: USART SYNCHRONOUS MASTER RECEPTION 1. Initialize the SPBRG register for the appropriate baud rate. (Section 12.1) 2. Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN.
PIC16C7X FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'. 1997 Microchip Technology Inc.
PIC16C7X 12.4 USART Synchronous Slave Mode Applicable Devices 72 73 73A 74 74A 76 77 Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 12.4.
PIC16C7X TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 18h RCSTA SPEN RX9 SREN CREN — FERR OERR 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000
PIC16C7X NOTES: DS30390E-page 116 1997 Microchip Technology Inc.
PIC16C7X 13.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. Applicable Devices 72 73 73A 74 74A 76 77 The analog-to-digital (A/D) converter module has five inputs for the PIC16C72/73/73A/76, and eight for the PIC16C74/74A/77.
PIC16C7X FIGURE 13-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 — bit7 U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D RE0(1) RE1(1) RE2(1) A A D D D D D A A D
PIC16C7X 3. 4. The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagrams of the A/D module are shown in Figure 13-3. 5. OR After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC16C7X 13.1 A/D Acquisition Requirements VDD = 5V → Rss = 7 kΩ Applicable Devices 72 73 73A 74 74A 76 77 Temp (application system max.) = 50°C VHOLD = 0 @ t = 0 For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 13-4.
PIC16C7X 13.2 Selecting the A/D Conversion Clock 13.3 Configuring Analog Port Pins Applicable Devices 72 73 73A 74 74A 76 77 Applicable Devices 72 73 73A 74 74A 76 77 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable.
PIC16C7X 13.4 A/D Conversions Applicable Devices 72 73 73A 74 74A 76 77 Note: Example 13-2 shows how to perform an A/D conversion. The RA pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the RA0 pin (channel 0). The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion.
PIC16C7X 13.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF Not all applications require a result with 8-bits of resolution, but may instead require a faster conversion time. The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same.
PIC16C7X 13.5 A/D Operation During Sleep Applicable Devices 72 73 73A 74 74A 76 77 The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion.
PIC16C7X 13.8 Use of the CCP Trigger FIGURE 13-5: A/D TRANSFER FUNCTION 04h 03h 02h 01h 256 LSb (full scale) 4 LSb 255 LSb 00h 3 LSb An A/D conversion can be started by the “special event trigger” of the CCP2 module (CCP1 on the PIC16C72 only). This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set).
PIC16C7X FIGURE 13-6: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No Yes A/D Clock = RC? SLEEP Yes Instruction? Start of A/D Conversion Delayed 1 Instruction Cycle Finish Conversion GO = 0 ADIF = 1 No No Yes Device in SLEEP? Abort Conversion GO = 0 ADIF = 0 Finish Conversion GO = 0 ADIF = 1 Wake-up Yes From Sleep? Wait 2 TAD No No Finish Conversion GO = 0 ADIF = 1 SLEEP Power-down A/D Stay in Sleep Power-down A/D Wait 2 TAD Wait 2 TAD TA
PIC16C7X TABLE 13-3: Address SUMMARY OF A/D REGISTERS, PIC16C73/73A/74/74A/76/77 Name INTCON 0Bh,8Bh, 10Bh,18Bh PIR1 0Ch Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 -
PIC16C7X NOTES: DS30390E-page 128 1997 Microchip Technology Inc.
PIC16C7X 14.0 SPECIAL FEATURES OF THE CPU Applicable Devices 72 73 73A 74 74A 76 77 What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16CXX family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16C7X FIGURE 14-2: CONFIGURATION WORD FOR PIC16C72/73A/74A/76/77 CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 bit13 CP0 PWRTE WDTE FOSC1 FOSC0 bit0 bit 13-8 5-4: CP1:CP0: Code Protection bits (2) 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enab
PIC16C7X 14.2 Oscillator Configurations TABLE 14-1: Applicable Devices 72 73 73A 74 74A 76 77 14.2.1 Ranges Tested: Mode OSCILLATOR TYPES XT The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC 14.2.
PIC16C7X 14.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 14-5 shows implementation of a parallel resonant oscillator circuit.
PIC16C7X 14.3 Reset A simplified block diagram of the on-chip reset circuit is shown in Figure 14-8. Applicable Devices 72 73 73A 74 74A 76 77 The PIC16CXX differentiates between various kinds of reset: • • • • • The PIC16C72/73A/74A/76/77 have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
PIC16C7X 14.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST), and Brown-out Reset (BOR) The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 14.4.3 Applicable Devices 72 73 73A 74 74A 76 77 14.4.1 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over.
PIC16C7X 14.4.5 14.4.6 TIME-OUT SEQUENCE On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 14-10, Figure 14-11, and Figure 14-12 depict time-out sequences on power-up.
PIC16C7X TABLE 14-6: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C72/73A/74A/76/77 POR BOR TO PD 0 0 0 1 1 1 1 1 x x x 0 1 1 1 1 1 0 x x 0 0 u 1 1 x 0 x 1 0 u 0 TABLE 14-7: Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP RESET CONDITION FOR SPECIAL REGISTERS Condition Program Counter STATUS Register PCON Register PCON Register PIC16C73/74 PIC16C72
PIC16C7X TABLE 14-8: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.
PIC16C7X TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.
PIC16C7X FIGURE 14-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1997 Microchip Technology Inc.
PIC16C7X FIGURE 14-13: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 14-14: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD D VDD 33k VDD 10k R R1 40k MCLR C MCLR PIC16CXX PIC16CXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that voltage drop across R does not violate the device’s electrical specification.
PIC16C7X 14.5 Interrupts Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C7X family has up to 12 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit.
PIC16C7X FIGURE 14-16: INTERRUPT LOGIC PSPIF PSPIE ADIF ADIE Wake-up (If in SLEEP mode) T0IF T0IE RCIF RCIE INTF INTE TXIF TXIE SSPIF SSPIE Interrupt to CPU RBIF RBIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts.
PIC16C7X 14.5.1 14.6 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt.
PIC16C7X 14.7 Watchdog Timer (WDT) prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. Applicable Devices 72 73 73A 74 74A 76 77 The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PIC16C7X 14.8 Power-down Mode (SLEEP) Applicable Devices 72 73 73A 74 74A 76 77 Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16C7X FIGURE 14-20: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 14.
PIC16C7X 15.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator.
PIC16C7X TABLE 15-2: PIC16CXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to
PIC16C7X 15.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [label] ADDLW Syntax: [label] ANDLW Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) C, DC, Z Status Affected: Z Status Affected: Encoding: 11 k 111x kkkk kkkk Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC16C7X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [label] BCF Syntax: [label] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
PIC16C7X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding: Description: 01 1 Cycles: 1(2) If Skip: Example bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is executed.
PIC16C7X CLRF Clear f Syntax: [label] CLRF Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1→Z Status Affected: Z Encoding: 00 f 0001 1fff ffff CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1→Z Status Affected: Z Encoding: 00 0001 0xxx xxxx Description: The contents of register 'f' are cleared and the Z bit is set. Description: W register is cleared. Zero bit (Z) is set.
PIC16C7X COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF Syntax: [ label ] DECFSZ f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (destination) Operation: Status Affected: Z (f) - 1 → (destination); skip if result = 0 Status Affected: None Encoding: Description: 00 f,d 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
PIC16C7X GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 2047 Operands: Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination) None Status Affected: Z Status Affected: Encoding: 10 GOTO k 1kkk kkkk kkkk Encoding: 00 INCF f,d 1010 dfff ffff Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>.
PIC16C7X INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Encoding: Description: 00 1 Cycles: 1(2) If Skip: 1111 dfff Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Q3 Q4 NoNoNoOperation Operation Operation Example ffff Q1 (2nd Cycle) Q1 Q2 HERE INCFSZ GOTO CONTINUE • • • Inclusive OR Literal with W Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Ope
PIC16C7X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. (f) → (destination) Operation: k → (W) Status Affected: Z Status Affected: None Encoding: IORWF 00 f,d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
PIC16C7X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS → PC, 1 → GIE Status Affected: None Encoding: 00 NOP 0000 0xx0 0000 RETFIE Description: No operation. Encoding: Words: 1 Description: Cycles: 1 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
PIC16C7X RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: TOS → PC Status Affected: None Status Affected: None Encoding: RETLW k Encoding: 11 Description: 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
PIC16C7X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: RLF 00 f,d 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register.
PIC16C7X SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD Operation: k - (W) → (W) Status Affected: C, DC, Z SLEEP Encoding: 11 110x kkkk kkkk Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register. The power-down status bit, PD is cleared. Time-out status bit, TO is set.
PIC16C7X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Operation: Status Affected: C, DC, Z (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None Encoding: Description: 00 1 Cycles: 1 Example 1: 0010 dfff ffff Subtract (2’s complement method) W register from register 'f'.
PIC16C7X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] Syntax: [label] Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .XOR. k → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: Z Operation: (W) .XOR. (f) → (destination) Status Affected: Z Encoding: 11 XORLW k 1010 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16C7X 16.0 DEVELOPMENT SUPPORT 16.
PIC16C7X 16.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC16C7X MPASM has the following features to assist in developing software for specific use applications. • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability. • Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems. • Supports Hex (default), Decimal and Octal source and listing formats.
Emulator Products Software Tools DS30390E-page 166 Programmers ✔ KEELOQ Evaluation Kit PICDEM-3 PICDEM-2 PICDEM-1 SEEVAL Designers Kit KEELOQ Programmer PRO MATE II Universal Programmer PICSTART Plus Low-Cost Universal Dev. Kit PICSTART Lite Ultra Low-Cost Dev. Kit Total Endurance Software Model ✔ ✔ ✔ fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C72 Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature ...............................................................................................................................
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.1 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +125˚C for extended, -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.2 DC Characteristics: PIC16LC72-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions 2.5 - 6.0 V RAM Data Retention Volt- VDR age (Note 1) - 1.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.3 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) PIC16LC72-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +125˚C for extended, -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.2. Sym Min Typ Max Units Conditions † VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.5 Timing Diagrams and Specifications FIGURE 17-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-2: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 17-1 for load conditions. TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 17-1 for load conditions. FIGURE 17-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 17-1 for load conditions. TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * † Tt0L Min Typ† Max 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 17-1 for load conditions. TABLE 17-6: Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 17-1 for load conditions TABLE 17-7: SPI MODE REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-9: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 17-1 for load conditions TABLE 17-8: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 THD:STA 92 TSU:STO 93 THD:STO Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 1997 Microchip Technology Inc.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-10: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 17-1 for load conditions I2C BUS DATA REQUIREMENTS TABLE 17-9: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 17-10: A/D CONVERTER CHARACTERISTICS: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) PIC16LC72-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ† Max Units Conditions — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF — — <±1 LSb VREF = VDD = 5.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-11: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-11: A/D CONVERSION REQUIREMENTS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73/74 Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature ............................................................................................................................... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.1 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.2 DC Characteristics: PIC16LC73/74-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 3.0 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.3 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D100 Characteristic Capacitive Loading Specs on Output Pins OSC2 pin Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.2. Sym Min Typ Max Units Conditions † COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.5 Timing Diagrams and Specifications FIGURE 18-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 18-2: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 18-1 for load conditions. TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 18-1 for load conditions. TABLE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 18-1 for load conditions. TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * † Tt0L Min Typ† Max 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 18-1 for load conditions. TABLE 18-6: Parameter No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min No Prescaler * † — — ns 10 — — ns 20 — — ns 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-7: PARALLEL SLAVE PORT TIMING (PIC16C74) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 18-1 for load conditions TABLE 18-7: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 18-1 for load conditions TABLE 18-8: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-9: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 18-1 for load conditions TABLE 18-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-10: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 18-1 for load conditions TABLE 18-10: I2C BUS DATA REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 18-1 for load conditions TABLE 18-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 18-13: A/D CONVERTER CHARACTERISTICS: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ† Max Units Conditions — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF VREF = VDD = 5.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-13: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 18-14: A/D CONVERSION REQUIREMENTS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73A/74A Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature ............................................................................................................................... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.1 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +125˚C for extended, -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.2 DC Characteristics: PIC16LC73A/74A-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 2.5 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.3 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +125˚C for extended, -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.2. Sym Min Typ Max Units Conditions † VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.5 Timing Diagrams and Specifications FIGURE 19-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 19-2: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 19-1 for load conditions. TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 19-1 for load conditions. FIGURE 19-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 19-1 for load conditions. TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * † Tt0L Min Typ† Max 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 19-1 for load conditions. TABLE 19-6: Param No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min No Prescaler — — ns 10 — — ns 20 — — ns 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-8: PARALLEL SLAVE PORT TIMING (PIC16C74A) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 19-1 for load conditions TABLE 19-7: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 19-1 for load conditions TABLE 19-8: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-10: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 19-1 for load conditions TABLE 19-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 19-1 for load conditions TABLE 19-10: I2C BUS DATA REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 19-1 for load conditions TABLE 19-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 19-13: A/D CONVERTER CHARACTERISTICS: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ† Max Units Conditions — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF — — <±1 LSb VREF = VDD = 5.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-14: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 19-14: A/D CONVERSION REQUIREMENTS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.0 ELECTRICAL CHARACTERISTICS FOR PIC16C76/77 Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature ............................................................................................................................... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-1: OSC RC XT CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C76-04 PIC16C77-04 VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 µA max. at 4V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 µA max. at 4V Freq: 4 MHz max. PIC16C76-10 PIC16C77-10 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 µA typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.1 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +125˚C for extended, -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.2 DC Characteristics: PIC16LC76/77-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 2.5 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.3 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) PIC16LC76/77-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +125˚C for extended, -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2. Sym Min Typ Max Units Conditions † VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.5 Timing Diagrams and Specifications FIGURE 20-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 20-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Typ† Max Fosc External CLKIN Frequency (Note 1) DC DC DC DC DC DC 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 20-1 for load conditions. TABLE 20-3: Param Sym No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 20-1 for load conditions. FIGURE 20-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 20-1 for load conditions. TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * † Tt0L Min Typ† Max 0.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 20-1 for load conditions. TABLE 20-6: Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-8: PARALLEL SLAVE PORT TIMING (PIC16C77) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 20-1 for load conditions TABLE 20-7: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSB SDO LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 20-1 for load conditions. FIGURE 20-10: SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 BIT6 - - - - - -1 MSB SDO LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure 20-1 for load conditions.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSB SDO LSB BIT6 - - - - - -1 77 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 20-1 for load conditions.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-8: Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-13: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 20-1 for load conditions TABLE 20-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 THD:STA 92 TSU:STO 93 THD:STO Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 1997 Microchip Technology Inc.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-14: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 20-1 for load conditions TABLE 20-10: I2C BUS DATA REQUIREMENTS Parameter No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 20-1 for load conditions TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-13: A/D CONVERTER CHARACTERISTICS: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) PIC16LC76/77-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ† Max Units Conditions — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF — — <±1 LSb VREF = VDD = 5.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-17: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 Tcy (TOSC/2) (1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 20-14: A/D CONVERSION REQUIREMENTS Param No.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 NOTES: DS30390E-page 240 1997 Microchip Technology Inc.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 21.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-3: TYPICAL IPD vs. VDD @ 25°C (WDT ENABLED, RC MODE) FIGURE 21-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 22 pF, T = 25°C 6.0 25 5.5 5.0 4.5 Fosc(MHz) IPD(µA) 20 15 10 R = 5k 4.0 3.5 3.0 R = 10k 2.5 2.0 5 1.5 1.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 2.5 VDD(Volts) FIGURE 21-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE) 35 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 0°C Cext = 100 pF, T = 25°C 2.4 2.2 R = 3.3k 2.0 20 1.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE) FIGURE 21-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) 1400 1200 30 25 Device NOT in Brown-out Reset 800 20 600 400 200 0 2.5 IPD(µA) IPD(µA) 1000 Device in Brown-out Reset 15 10 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 5 6.0 0 2.5 The shaded region represents the built-in hysteresis of the brown-out reset circuitry. FIGURE 21-9: MAXIMUM IPD vs.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V IDD(µA) 1400 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency(MHz) 3.5 4.0 4.5 Shaded area is beyond recommended range FIGURE 21-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V IDD(µA) Data based on matrix samples.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(µA) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz) FIGURE 21-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C) 1600 6.0V 1400 5.0V 1200 4.5V 4.0V 1000 IDD(µA) 3.5V 3.0V 800 2.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V IDD(µA) 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 21-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C) 1200 6.0V 5.5V 5.0V 4.5V 4.0V 800 3.5V IDD(µA) Data based on matrix samples. See first page of this section for details. 1000 3.0V 600 2.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE) FIGURE 21-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD 600 4.0 3.5 3.0 gm(mA/V) 4.0V 400 IDD(µA) Max -40°C 5.0V 500 3.0V 300 200 2.5 Typ 25°C 2.0 Min 85°C 1.5 1.0 100 0.5 100 pF RC OSCILLATOR FREQUENCIES 100 300 pF 5k 4.12 MHz ± 1.4% 10k 2.35 MHz ± 1.4% 100k 268 kHz ± 1.1% 5.5 6.0 6.5 7.0 70 60 1.80 MHz ± 1.0% 1.27 MHz ± 1.0% 10k 688 kHz ± 1.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25°C) FIGURE 21-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25°C) 3.5 70 3.0 60 50 Startup Time(ms) Startup Time(Seconds) 2.5 2.0 32 kHz, 33 pF/33 pF 1.5 1.0 40 200 kHz, 68 pF/68 pF 30 200 kHz, 47 pF/47 pF 20 1 MHz, 15 pF/15 pF 10 0.5 4 MHz, 15 pF/15 pF 200 kHz, 15 pF/15 pF 0.0 2.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 6.0 4.0 4.5 VDD(Volts) 5.0 5.5 6.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25°C) FIGURE 21-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25°C) 1800 1600 6.0V 1400 5.5V 120 100 5.0V 1200 4.5V 1000 4.0V 60 40 20 0 0 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V IDD(µA) IDD(µA) 80 3.5V 800 3.0V 600 2.5V 400 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 21-26: MAXIMUM IDD vs.
PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25°C) 7.0 FIGURE 21-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40°C TO 85°C) 7.0 6.0 6.0 5.0 IDD(mA) IDD(mA) 5.0 4.0 3.0 2.0 1.0 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4.0 3.0 2.0 1.0 4 6 8 10 12 Frequency(MHz) 14 16 18 20 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4 6 8 10 12 14 16 18 20 Data based on matrix samples. See first page of this section for details.
PIC16C7X 22.0 PACKAGING INFORMATION 22.1 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil)(JW) N C E1 E eA eB α Pin #1 Indicator Area D S1 S Base Plane Seating Plane L B1 A3 A2 A A1 e1 B D1 Package Group: Ceramic Side Brazed Dual In-Line (CER) Millimeters Inches Symbol α A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 Min Max 0° 3.937 1.016 2.921 1.930 0.406 1.219 0.228 35.204 32.893 7.620 7.366 2.413 7.366 7.594 3.302 28 1.143 0.533 10° 5.030 1.524 3.506 2.388 0.508 1.
PIC16C7X 22.2 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW) N E1 E α C Pin No. 1 Indicator Area eA eB D S S1 Base Plane Seating Plane L B1 A1 A3 A A2 e1 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol Min Max α 0° A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 4.318 0.381 3.810 3.810 0.355 1.270 0.203 51.435 48.260 15.240 12.954 2.540 14.986 15.240 3.175 40 1.016 0.381 DS30390E-page 252 Inches Notes Min Max 10° 0° 10° 5.715 1.778 4.699 4.
PIC16C7X 22.3 28-Lead Plastic Dual In-line (300 mil) (SP) N α E1 E C eA eB Pin No. 1 Indicator Area B2 D B1 S Base Plane Seating Plane L Detail A B3 A1 A2 A e1 B Detail A D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max α 0° A A1 A2 B B1 B2 B3 C D D1 E E1 e1 eA eB L N S 3.632 0.381 3.175 0.406 1.016 0.762 0.203 0.203 34.163 33.020 7.874 7.112 2.540 7.874 8.128 3.175 28 0.584 1997 Microchip Technology Inc. Inches Notes Min Max 10° 0° 10° 4.572 – 3.556 0.
PIC16C7X 22.4 40-Lead Plastic Dual In-line (600 mil) (P) N α E1 E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max α 0° A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.175 0.355 1.270 0.203 51.181 48.260 15.240 13.462 2.489 15.240 15.240 2.921 40 1.270 0.508 DS30390E-page 254 Inches Notes Min Max 10° 0° 10° 5.080 – 4.064 0.559 1.778 0.381 52.197 48.260 15.875 13.970 2.
PIC16C7X 22.5 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) e B h x 45° N Index Area E H α C Chamfer h x 45° L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max α 0° 8° 0° 8° A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 17.703 7.416 1.270 10.007 0.381 0.406 28 – 2.642 0.300 0.483 0.318 18.085 7.595 1.270 10.643 0.762 1.143 28 0.102 0.093 0.004 0.014 0.009 0.697 0.292 0.050 0.394 0.
PIC16C7X 22.6 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) N Index area E H α C L 1 2 3 B e A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Symbol Min Max Inches Notes Min Max α 0° 8° 0° 8° A A1 B C D E e H L N CP 1.730 0.050 0.250 0.130 10.070 5.200 0.650 7.650 0.550 28 - 1.990 0.210 0.380 0.220 10.330 5.380 0.650 7.900 0.950 28 0.102 0.068 0.002 0.010 0.005 0.396 0.205 0.026 0.301 0.022 28 - 0.078 0.008 0.015 0.009 0.407 0.212 0.
PIC16C7X 22.7 44-Lead Plastic Leaded Chip Carrier (Square)(PLCC) D -A- D1 -D- 3 -F- 0.812/0.661 N Pics .032/.026 1.27 .050 2 Sides 0.177 .007 S B D-E S -HA A1 3 D3/E3 D2 0.38 .015 3 -G- 8 F-G S 0.177 .007 S B A S 2 Sides 9 0.101 Seating .004 Plane D -C- 4 E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.254 .010 Max 2 0.254 .010 Max 11 -H- 11 0.508 .020 0.508 .020 -H- 2 0.812/0.661 3 .032/.026 1.524 .060 Min 6 6 -C1.651 .065 1.651 .065 R 1.14/0.64 .
PIC16C7X 22.8 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ) 4 D D1 5 0.20 M C A-B S D S 0.20 M H A-B S D S 7 0.20 min. 0.05 mm/mm A-B D3 0.13 R min. Index area 6 9 PARTING LINE 0.13/0.30 R α b L C E3 E1 E 1.60 Ref. 0.20 M C A-B S D S 4 TYP 4x 10 e 0.20 M H A-B S B D S 5 7 0.
PIC16C7X 22.9 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ) D D1 1.0ø (0.039ø) Ref. Pin#1 2 11°/13°(4x) Pin#1 2 E 0° Min E1 Θ 11°/13°(4x) Detail B e 3.0ø (0.118ø) Ref. Option 1 (TOP side) A2 A L Detail A R 0.08/0.20 Option 2 (TOP side) A1 Detail B R1 0.08 Min Base Metal Lead Finish b L c 1.00 Ref. Gage Plane 0.250 c1 L1 1.00 Ref b1 Detail A S 0.
PIC16C7X 22.10 Package Marking Information 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX PIC16C72 20I/SS025 AABBCAE 9517SBP 28-Lead PDIP (Skinny DIP) Example MMMMMMMMMMMM XXXXXXXXXXXXXXX AABBCDE PIC16C73-10/SP AABBCDE 28-Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX XXXXXXXXXXX AABBCDE MMMMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXXXX AABBCDE MM...M XX...
PIC16C7X Package Marking Information (Cont’d) 40-Lead PDIP Example MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX AABBCDE 40-Lead CERDIP Windowed PIC16C74-04/P 9512CAA Example MMMMMMMMM XXXXXXXXXXX XXXXXXXXXXX AABBCDE 44-Lead PLCC 44-Lead MQFP PIC16C74 -10/L AABBCDE Example PIC16C74 -10/PQ MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE AABBCDE MM...M XX...
PIC16C7X Package Marking Information (Cont’d) 44-Lead TQFP Example MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE Legend: PIC16C74A -10/TQ AABBCDE MM...M XX...X AA BB C D1 E Note: Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01’) Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A.
PIC16C7X APPENDIX A: APPENDIX B: COMPATIBILITY The following are the list of modifications over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before).
PIC16C7X APPENDIX C: WHAT’S NEW APPENDIX D: WHAT’S CHANGED Added the following devices: Minor changes, spelling and grammatical changes. • PIC16C76 • PIC16C77 Added the following note to the USART section. This note applies to all devices except the PIC16C76 and PIC16C77. Removed the PIC16C710, PIC16C71, PIC16C711 from this datasheet. Added PIC16C76 and PIC16C77 devices. The PIC16C76/77 devices have 368 bytes of data memory distributed in 4 banks and 8K of program memory in 4 pages.
PIC16C7X APPENDIX E: PIC16/17 MICROCONTROLLERS E.
PIC16C7X E.3 PIC16C15X Family of Devices PIC16C154 Clock Memory PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 20 20 20 20 20 20 EPROM Program Memory (x12 words) 512 — 1K — 2K — ROM Program Memory (x12 words) — 512 — 1K — 2K 73 RAM Data Memory (bytes) 25 25 25 25 73 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 12 12 Voltage Range (Volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.
PIC16C7X E.5 PIC16C55X Family of Devices PIC16C556(1) PIC16C554 Clock Memory 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K Data Memory (bytes) 80 80 128 Timer Module(s) TMR0 TMR0 TMR0 — — — — — — Peripherals Comparators(s) Internal Reference Voltage Features PIC16C558 Maximum Frequency of Operation (MHz) Interrupt Sources 3 3 3 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.
PIC16C7X E.
PIC16C7X E.8 PIC16C8X Family of Devices PIC16F83 Clock Memory Peripherals Features PIC16CR83 PIC16F84 PIC16CR84 Maximum Frequency of Operation (MHz) 10 10 10 10 Flash Program Memory 512 — 1K — EEPROM Program Memory — — — — ROM Program Memory — 512 — 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 Timer Module(s) TMR0 TMR0 TMR0 TMR0 Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.
PIC16C7X E.
PIC16C7X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55.
PIC16C7X NOTES: DS30390E-page 272 1997 Microchip Technology Inc.
PIC16C7X INDEX A A/D Accuracy/Error ......................................................... 124 ADCON0 Register .................................................... 117 ADCON1 Register .................................................... 118 ADIF bit .................................................................... 119 Analog Input Model Block Diagram .......................... 120 Analog-to-Digital Converter ...................................... 117 Block Diagram .....................................
PIC16C7X CCP2IF bit .......................................................................... 38 CCPR1H Register ............................................ 25, 27, 29, 71 CCPR1L Register ......................................................... 29, 71 CCPR2H Register ............................................ 25, 27, 29, 71 CCPR2L Register ............................................. 25, 27, 29, 71 CCPxM0 bit ........................................................................ 72 CCPxM1 bit ......
PIC16C7X Instruction Set ADDLW .................................................................... 149 ADDWF .................................................................... 149 ANDLW .................................................................... 149 ANDWF .................................................................... 149 BCF .......................................................................... 150 BSF ..........................................................................
PIC16C7X PICSTART Low-Cost Development System .................... 163 PIE1 Register ............................................................... 29, 33 PIE2 Register ............................................................... 29, 37 Pin Compatible Devices ................................................... 271 Pin Functions MCLR/VPP ...................................................... 13, 14, 15 OSC1/CLKIN .................................................. 13, 14, 15 OSC2/CLKOUT ..................
PIC16C7X Registers FSR Summary ........................................................... 29 INDF Summary ........................................................... 29 Initialization Conditions ............................................ 136 INTCON Summary ........................................................... 29 Maps PIC16C72 .......................................................... 21 PIC16C73 .......................................................... 21 PIC16C73A ................................
PIC16C7X Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 ............................................................ 79, 84 Synchronous Serial Port Module ........................................ 77 Synchronous Serial Port Status Register ........................... 83 T T0CS bit ............................................................................. 31 T1CKPS0 bit ...................................................................... 65 T1CKPS1 bit ............................................
PIC16C7X U UA ................................................................................ 78, 83 Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................................ 99 Update Address bit, UA ............................................... 78, 83 USART Asynchronous Mode ................................................ 106 Asynchronous Receiver ........................................... 108 Asynchronous Reception ..................
PIC16C7X LIST OF FIGURES Figure 8-1: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 4-1: Figure 8-2: Figure 9-1: Figure 9-2: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 4-13: Figure 4-14: Figure 4-15: Figure 4-16: Figure 4-17: Figure 4-18: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: Figure 5-8: Figure 5-9: Figure 5-10: Figure 5-11: Figure 5-12: Figure 5-13: F
PIC16C7X Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8: Figure 12-9: Figure 12-10: Figure 12-11: Figure 12-12: Figure 12-13: Figure 12-14: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 13-5: Figure 13-6: Figure 14-1: Figure 14-2: Figure 14-3: Figure 14-4: Figure 14-5: Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 14-11: Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 14-20: Figure 14-21: Fig
PIC16C7X Figure 20-9: Figure 20-10: Figure 20-11: Figure 20-12: Figure 20-13: Figure 20-14: Figure 20-15: Figure 20-16: Figure 20-17: Figure 21-1: Figure 21-2: Figure 21-3: Figure 21-4: Figure 21-5: Figure 21-6: Figure 21-7: Figure 21-8: Figure 21-9: Figure 21-10: Figure 21-11: Figure 21-12: Figure 21-13: Figure 21-14: Figure 21-15: Figure 21-16: Figure 21-17: Figure 21-18: Figure 21-19: Figure 21-20: Figure 21-21: Figure 21-22: Figure 21-23: Figure 21-24: Figure 21-25: Figure 21-26: SPI Master Mode Tim
PIC16C7X LIST OF TABLES Table 12-8: Table 1-1: Table 3-1: Table 3-2: Table 3-3: Table 4-1: Table 12-9: Table 4-2: Table 4-3: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 5-8: Table 5-9: Table 5-10: Table 5-11: Table 7-1: Table 8-1: Table 8-2: Table 9-1: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 10-5: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 11-5: Table 12-1: Table 12-2: Table 12-3: Table 12-4: Table 12-5: Table 12-6: Table 12-7: PIC16C7XX F
PIC16C7X Table 18-2: Table 18-3: Table 18-4: Table 18-5: Table 18-6: Table 18-7: Table 18-8: Table 18-9: Table 18-10: Table 18-11: Table 18-12: Table 18-13: Table 18-14: Table 19-1: Table 19-2: Table 19-3: Table 19-4: Table 19-5: Table 19-6: Table 19-7: Table 19-8: Table 19-9: Table 19-10: Table 19-11: Table 19-12: Table 19-13: Table 19-14: external Clock Timing Requirements.......................................... 189 CLKOUT and I/O Timing Requirements..........................................
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PIC16C7X PIC16C7X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. Examples PART NO.
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
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