Datasheet

 1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 95
PIC16C62B/72A
FIGURE 13-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 13-7: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Symbol Characteristic Min Typ† Max Units Conditions
70
TssL2scH,
TssL2scL
SS to SCK or SCK input TCY —— ns
71
TscH SCK input high time
(slave mode)
Continuous 1.25TCY + 30 — — ns
71A
Single Byte 40 — — ns Note 1
72
TscL SCK input low time
(slave mode)
Continuous 1.25TCY + 30 — — ns
72A
Single Byte 40 — — ns Note 1
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge 100 — — ns
73A
TB2B Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40 — — ns Note 1
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge 100 — — ns
75
TdoR SDO data output rise time
PIC16CXX
—1025ns
PIC16LCXX
—2045ns
76
TdoF SDO data output fall time — 10 25 ns
78
TscR SCK output rise time
(master mode)
PIC16CXX
—1025ns
PIC16LCXX
—2045ns
79
TscF SCK output fall time (master mode) — 10 25 ns
80
TscH2doV,
TscL2doV
SDO data output valid
after SCK edge
PIC16CXX
——50ns
PIC16LCXX
— — 100 ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN
LSb IN
BIT6 - - - -1
Note: Refer to Figure 13-4 for load conditions.