Datasheet
PIC16C62B/72A
DS35008C-page 52 Preliminary 1998-2013 Microchip Technology Inc.
9.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 9-2. The source
impedance (R
S) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor C
HOLD. The sampling switch (RSS)
impedance varies over the device voltage (V
DD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
k. After the analog input channel is selected
(changed), this acquisition must pass before the con-
version can be started.
To calculate the minimum acquisition time, T
ACQ, see
Equation 9-1. This equation calculates the acquisition
time to within 1/2 LSb error (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified accuracy.
In general;
Assuming R
S = 10k
Vdd = 3.0V (R
SS = 10k
Te mp. = 5 0C (122F)
T
ACQ 13.0 Sec
By increasing V
DD and reducing RS and Temp., TACQ
can be substantially reduced.
FIGURE 9-2: ANALOG INPUT MODEL
EQUATION 9-1: ACQUISITION TIME
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
TACQ =
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
TAMP = 5S
T
C = - (51.2pF)(1k + RSS + RS) In(1/511)
T
COFF = (Temp -25C)(0.05S/C)
CPIN
VA
Rs
ANx
5 pF
V
DD
VT = 0.6V
VT = 0.6V
I leakage
R
IC 1k
Sampling
Switch
SS
R
SS
CHOLD
= DAC capacitance
V
SS
6V
R
SS
5V
4V
3V
2V
567891011
(k)
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions