Datasheet

PIC16C62B/72A
DS35008C-page 32 Preliminary  1998-2013 Microchip Technology Inc.
6.1 Timer2 Operation
The Timer2 output is also used by the CCP module to
generate the PWM "On-Time", and the PWM period
with a match with PR2.
The TMR2 register is readable and writable, and is
cleared on any device reset.
The input clock (F
OSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit post-
scaler (which gives a 1:1 to 1:16 scaling) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR
reset,
Watchdog Timer reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
6.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
6.3 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate shift clock.
TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on
all other
resets
0Bh,8Bh INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF
0000 000x 0000 000u
0Ch PIR1
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF
-00- 0000 0000 0000
8Ch PIE1
— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE
-0-- 0000 0000 0000
11h TMR2 Timer2 module’s register
0000 0000 0000 0000
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000
92h PR2 Timer2 Period Register
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.