Datasheet

PIC16C62B/72A
DS35008C-page 102 Preliminary  1998-2013 Microchip Technology Inc.
FIGURE 13-17: A/D CONVERSION TIMING
TABLE 13-14: A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Unit
s
Conditions
130
TAD A/D clock period
PIC16CXX
1.6 — — sTOSC based, VREF  3.0V
PIC16LCXX
2.0 — — sTOSC based, VREF full range
PIC16CXX
2.0 4.0 6.0 sA/D RC Mode
PIC16LCXX
3.0 6.0 9.0 sA/D RC Mode
131
TCNV Conversion time (not including S/H
time) (Note 1)
11 — 11 TAD
132
TACQ Acquisition time Note 2
5*
20
—
—
—
s
s The minimum time is the
amplifier settling time. This
may be used if the "new" input
voltage has not changed by
more than 1 LSb (i.e., 20.0 mV
@ 5.12V) from the last sam-
pled voltage (as stated on
C
HOLD).
134
TGO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is
selected as RC, a time of T
CY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135
Tswc Switching from convert  sample
time
1.5 — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 9.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Tosc/2) (1)
7 6 5432 10
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
1 TCY
134