Datasheet
PIC16C62B/72A
DS35008C-page 10 Preliminary 1998-2013 Microchip Technology Inc.
Bank 1
80h INDF
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL
(1)
Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS
(1)
IRP
(5)
RP1
(5)
RP0 TO PD ZDCC0001 1xxx 000q quuu
84h FSR
(1)
Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA
— — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h-89h — Unimplemented — —
8Ah PCLATH
(1,2)
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON
(1)
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1
—ADIE
(3)
— — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh — Unimplemented — —
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh-91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I
2
C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
95h-9Eh — Unimplemented — —
9Fh ADCON1
(3)
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR
and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(4)