PIC16C62B/72A 28-Pin 8-Bit CMOS Microcontrollers Pin Diagram • High-performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches, which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) • Interrupt capability • Eight level deep hardware stack • Direct, indirect, and relative addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT)
PIC16C62B/72A Pin Diagrams MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL •1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16C62B SDIP, SOIC, SSOP, Windowed CERDIP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA Key Features PIC® Mid-Range Reference Manual (DS33023) PIC16C62B PIC16C72A Operating Frequency DC - 20 MHz DC - 20 MHz Resets (and Delays) POR, BOR (PWRT, OST) POR
PIC16C62B/72A Table of Contents 1.0 Device Overview .................................................................................................................................................... 5 2.0 Memory Organization ............................................................................................................................................. 7 3.0 I/O Ports ...............................................................................................................................
PIC16C62B/72A NOTES: DS35008C-page 4 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 1.0 DEVICE OVERVIEW ommended reading for a better understanding of the device architecture and operation of the peripheral modules. This document contains device-specific information. Additional information may be found in the PIC® MCU Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website.
PIC16C62B/72A TABLE 1-1 PIC16C62B/PIC16C72A PINOUT DESCRIPTION DIP Pin# SOIC Pin# I/O/P Type OSC1/CLKIN 9 9 I OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device.
PIC16C62B/72A 2.0 MEMORY ORGANIZATION FIGURE 2-1: There are two memory blocks in each of these microcontrollers. Each block (Program Memory and Data Memory) has its own bus, so that concurrent access can occur. PC<12:0> CALL, RETURN RETFIE, RETLW Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). 2.
PIC16C62B/72A 2.2 Data Memory Organization FIGURE 2-2: The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.
PIC16C62B/72A 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1 Addr The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
PIC16C62B/72A TABLE 2-1 Addr SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C62B/72A 2.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
PIC16C62B/72A 2.2.2.2 OPTION_REG REGISTER Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16C62B/72A 2.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register, which contains various interrupt enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16C62B/72A 2.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. REGISTER 2-4: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16C62B/72A 2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts. REGISTER 2-5: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C62B/72A 2.2.2.6 PCON REGISTER Note: The Power Control register (PCON) contains flag bits to allow differentiation between a Power-on Reset (POR), Brown-Out Reset (BOR) and resets from other sources. . REGISTER 2-6: On Power-on Reset, the state of the BOR bit is unknown and is not predictable. If the BODEN bit in the configuration word is set, the user must first set the BOR bit on a POR, and check it on subsequent resets. If BOR is cleared while POR remains set, a Brown-out reset has occurred.
PIC16C62B/72A 2.3 PCL and PCLATH 2.4 The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register and is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly accessible. All updates to the PCH register go through the PCLATH register. 2.3.1 STACK The stack allows any combination of up to 8 program calls and interrupts to occur.
PIC16C62B/72A 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-1: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). NEXT Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
PIC16C62B/72A 3.0 I/O PORTS FIGURE 3-1: Some I/O port pins are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PIC® MCU Mid-Range Reference Manual, (DS33023). 3.
PIC16C62B/72A TABLE 3-1 PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input(1) RA1/AN1 bit1 TTL Input/output or analog input(1) RA2/AN2 bit2 TTL Input/output or analog input(1) RA3/AN3/VREF bit3 TTL RA4/T0CKI bit4 ST Input/output or analog input(1) or VREF(1) Input/output or external clock input for Timer0 Output is open drain type bit5 TTL Input/output or slave select input for synchronous serial port or analog input(1) RA5/SS/AN4 Legend: TTL = T
PIC16C62B/72A 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, (i.e., put the contents of the output latch on the selected pin). Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature.
PIC16C62B/72A TABLE 3-3 PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change).
PIC16C62B/72A 3.3 PORTC and the TRISC Register PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5).
PIC16C62B/72A TABLE 3-5 PORTC FUNCTIONS Name Bit# RC0/T1OSO/T1CKI bit0 Buffer Function Type ST TRISC Override Input/output port pin or Timer1 oscillator output/Timer1 clock input Yes RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input Yes RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output No RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes.
PIC16C62B/72A 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the Electrical Specifications section of this manual, and in the PIC® MCU Mid-Range Reference Manual, (DS33023). The Timer0 module timer/counter has the following features: • 8-bit timer/counter - Read and write - INT on overflow • 8-bit software programmable prescaler • INT or EXT clock select - EXT clock edge select 4.
PIC16C62B/72A 4.2.1 4.3 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program execution). Note: The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt.
PIC16C62B/72A 5.0 TIMER1 MODULE 5.1 The Timer1 module timer/counter has the following features: • • • • • 16-bit timer/counter Readable and writable Internal or external clock select Interrupt on overflow from FFFFh to 0000h Reset from CCP module trigger Timer1 Operation Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).
PIC16C62B/72A FIGURE 5-1: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1H Synchronized clock input 0 TMR1 TMR1L 1 TMR1ON on/off T1SYNC T1OSC RC0/T1OSO/T1CKI RC1/T1OSI 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Synchronize Prescaler 1, 2, 4, 8 det 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
PIC16C62B/72A 5.2 5.3 Timer1 Oscillator Timer1 Interrupt A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). When the Timer1 oscillator is enabled, RC0 and RC1 pins become T1OSO and T1OSI inputs, overriding TRISC<1:0>. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h.
PIC16C62B/72A NOTES: DS35008C-page 30 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 6.0 TIMER2 MODULE Additional information on timer modules is available in the PIC® MCU Mid-Range Reference Manual, (DS33023).
PIC16C62B/72A 6.1 Timer2 Operation 6.2 The Timer2 output is also used by the CCP module to generate the PWM "On-Time", and the PWM period with a match with PR2. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).
PIC16C62B/72A 7.0 CAPTURE/COMPARE/PWM (CCP) MODULE Additional information on the CCP module is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). The CCP (Capture/Compare/PWM) module contains a 16-bit register, which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave duty cycle register. Table 7-1 shows the timer resources of the CCP module modes.
PIC16C62B/72A 7.1 Capture Mode 7.1.4 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register, when an event occurs on pin RC2/CCP1. An event is defined as: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit ,CCP1IF (PIR1<2>), is set. It must be cleared in software.
PIC16C62B/72A 7.2 7.2.1 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • driven High • driven Low • remains Unchanged FIGURE 7-2: COMPARE MODE OPERATION BLOCK DIAGRAM TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 7.2.
PIC16C62B/72A 7.3 PWM Mode 7.3.1 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 7-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16C62B/72A 7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM on-time by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
PIC16C62B/72A NOTES: DS35008C-page 38 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 8.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 8.1 SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16C62B/72A TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION Value on POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 8Ch 13h SSPBUF 14h SSPCON WCOL 94h SSPSTAT 85h TRISA 87h TRISC Synchronous Serial Port Receive Buffer/Transmit
PIC16C62B/72A 8.3 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to support firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA).
PIC16C62B/72A 8.3.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16C62B/72A 8.3.1.2 RECEPTION When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
PIC16C62B/72A 8.3.1.3 TRANSMISSION shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 8-4). When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and the CKP will be cleared by hardware, holding SCL low.
PIC16C62B/72A 8.3.2 8.3.3 MASTER OPERATION MULTI-MASTER OPERATION In multi-master operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions.
PIC16C62B/72A REGISTER 8-1: R/W-0 R/W-0 SMP CKE SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R-0 R-0 R-0 R-0 R-0 R-0 D/A P S R/W UA BF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode I2C Mode This
PIC16C62B/72A REGISTER 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indica
PIC16C62B/72A NOTES: DS35008C-page 48 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 9.0 Note: ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE This section applies to the PIC16C72A only. Additional information on the A/D module is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). The A/D module has three registers. These registers are: The analog-to-digital (A/D) converter module has five input channels. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter).
PIC16C62B/72A REGISTER 9-2:ADCON1 REGISTER (ADDRESS 9Fh) U-0 — bit7 U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D VREF VDD RA3 VDD RA3 VDD RA3 VDD A =
PIC16C62B/72A When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit, ADCON0<2>, is cleared, and the A/D interrupt flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 9-1. 1. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. 2.
PIC16C62B/72A 9.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC16C62B/72A 9.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • 2TOSC 8TOSC 32TOSC Internal RC oscillator The A/D module can operate during sleep mode, but the RC oscillator must be selected as the A/D clock source prior to the SLEEP instruction.
PIC16C62B/72A 9.4 Note: 9.5 A/D Conversions GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead. The appropriate analog input channel must be selected and the minimum acquisition time must pass before the “special event trigger” sets the GO/DONE bit (starts a conversion). The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
PIC16C62B/72A 10.0 SPECIAL FEATURES OF THE CPU other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only and is designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. The PIC16C62B/72A devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16C62B/72A 10.2 Oscillator Configurations 10.2.1 OSCILLATOR TYPES TABLE 10-1 Ranges Tested: The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC 10.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.
PIC16C62B/72A 10.2.3 RC OSCILLATOR 10.3 For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation.
PIC16C62B/72A FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset S BODEN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. DS35008C-page 58 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 10.4 10.5 Power-On Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified (SVDD, parameter D004). For a slow rise time, see Figure 10-6.
PIC16C62B/72A 10.8 Time-out Sequence Table 10-5 shows the reset conditions for the STATUS, PCON and PC registers, while Table 10-6 shows the reset conditions for all the registers. When a POR reset occurs, the PWRT delay starts (if enabled). When PWRT ends, the OST counts 1024 oscillator cycles (LP, XT, HS modes only). When OST completes, the device comes out of reset. The total time-out will vary based on oscillator configuration and the status of the PWRT.
PIC16C62B/72A TABLE 10-6 Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt W 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu INDF 62B 72A N/A N/A N/A TMR0 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PCL 62B 72A 0000h 0000h PC + 1(2) STATUS 62B 72A 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PORTA(4) 62B 72A --0x 0000 --0u 0000 --uu uuuu POR
PIC16C62B/72A 10.10 Interrupts The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits.
PIC16C62B/72A 10.10.1 INT INTERRUPT 10.11 The external interrupt on RB0/INT pin is edge triggered: either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt.
PIC16C62B/72A 10.12 Watchdog Timer (WDT) The WDT time-out period (TWDT, parameter #31) is multiplied by the prescaler ratio, when the prescaler is assigned to the WDT. The prescaler assignment (assigned to either the WDT or Timer0) and prescaler ratio are set in the OPTION_REG register. The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PIC16C62B/72A 10.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low or hi-impedance).
PIC16C62B/72A FIGURE 10-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 10.
PIC16C62B/72A 11.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 11-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode field descriptions.
PIC16C62B/72A TABLE 11-2 PIC16CXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move
PIC16C62B/72A 11.1 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [label] ADDLW Syntax: [label] ANDWF Operands: 0 k 255 Operands: 0 f 127 d Operation: (W) .AND. (f) (destination) Status Affected: Z Description: AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
PIC16C62B/72A BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [label] BTFSS f,b Syntax: [label] CLRF Operands: 0 f 127 0b<7 Operands: 0 f 127 Operation: Operation: skip if (f) = 1 00h (f) 1Z Status Affected: None Status Affected: Z Description: If bit 'b' in register 'f' is '0', then the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
PIC16C62B/72A COMF Complement f GOTO Unconditional Branch Syntax: [ label ] COMF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 2047 Operation: (f) (destination) Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. Description: GOTO is an unconditional branch.
PIC16C62B/72A IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: 0 k 255 Operation: (W) .OR. k (W) Operation: k (W) Status Affected: Z Status Affected: None Description: The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register. Description: The eight bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s.
PIC16C62B/72A RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS PC, 1 GIE 0 f 127 d [0,1] Operation: See description below None Status Affected: C Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
PIC16C62B/72A SUBLW Subtract W from Literal XORLW Exclusive OR Literal with W Syntax: [ label ] Syntax: [label] Operands: 0 k 255 Operands: 0 k 255 Operation: k - (W) W) Operation: (W) .XOR. k W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register. Description: The contents of the W register are XOR’ed with the eight bit literal 'k'.
PIC16C62B/72A 12.
PIC16C62B/72A MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and modification of library files. MPLINK features include: • MPLINK works with MPASM and MPLAB-C17 and MPLAB-C18.
PIC16C62B/72A stand-alone mode the PRO MATE II can read, verify or program PIC devices. It can also set code-protect bits in this mode. 12.11 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus supports all PIC devices with up to 40 pins.
PIC16C62B/72A and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 12.
1998-2013 Microchip Technology Inc.
PIC16C62B/72A NOTES: DS35008C-page 80 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 13.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.
PIC16C62B/72A FIGURE 13-1: PIC16C62B/72A-20 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC16CXXX PIC16CXXX-20 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 20 MHz Frequency FIGURE 13-2: PIC16LC62B/72A AND PIC16C62B/72A/JW VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V 4.5 V 4.0 V PIC16LCXXX-04 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz 10 MHz Frequency FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
PIC16C62B/72A FIGURE 13-3: PIC16C62B/72A-04 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC16CXXX-04 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz Frequency 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 13.1 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units 4.0 4.5 5.5 5.5 5.
PIC16C62B/72A 13.2 DC Characteristics: PIC16LC62B/72A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial Min Typ† Max Units 2.5 VBOR* - 5.5 5.5 V V Conditions D001 VDD Supply Voltage D002* VDR RAM Data Retention Voltage (Note 1) - 1.
PIC16C62B/72A 13.3 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) PIC16LC62B/72A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Sym Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial -40°C TA +125°C for extended Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.
PIC16C62B/72A DC CHARACTERISTICS Param No. Sym D083 Characteristic OSC2/CLKOUT (RC osc mode) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial -40°C TA +125°C for extended Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2 Min Typ† Max Units Conditions - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C - - 0.6 V IOL = 1.6 mA, VDD = 4.
PIC16C62B/72A 13.4 AC (Timing) Characteristics 13.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16C62B/72A 13.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 13-1 apply to all timing specifications unless otherwise noted. Figure 13-4 specifies the load conditions for the timing specifications.
PIC16C62B/72A 13.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 13-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 13-2: Param No.
PIC16C62B/72A FIGURE 13-6: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 13-4 for load conditions. TABLE 13-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym No.
PIC16C62B/72A FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 13-4 for load conditions. FIGURE 13-8: BROWN-OUT RESET TIMING BVDD VDD TABLE 13-4: Param No.
PIC16C62B/72A FIGURE 13-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 13-4 for load conditions. TABLE 13-5: Param No.
PIC16C62B/72A FIGURE 13-10: CAPTURE/COMPARE/PWM TIMINGS CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 13-4 for load conditions. TABLE 13-6: Param No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS Sym TccL TccH Characteristic CCP1 input low time CCP1 input high time Min No Prescaler With Prescaler 0.5TCY + 20 — — ns PIC16CXX 10 — — ns PIC16LCXX 20 — — ns 0.
PIC16C62B/72A FIGURE 13-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 13-4 for load conditions. TABLE 13-7: Param. No.
PIC16C62B/72A FIGURE 13-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO LSb BIT6 - - - - - -1 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: TABLE 13-8: Param. No. 71 EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Symbol TscH 71A 72 Refer to Figure 13-4 for load conditions. TscL 72A Characteristic Min Typ† Max Units SCK input high time (slave mode) Continuous 1.
PIC16C62B/72A FIGURE 13-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: TABLE 13-9: Param. No. Refer to Figure 13-4 for load conditions.
PIC16C62B/72A FIGURE 13-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 NOTE: Refer to Figure 13-4 for load conditions. TABLE 13-10: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. No. Symbol Characteristic Min TCY Typ† Max Units 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (slave mode) Continuous 1.
PIC16C62B/72A FIGURE 13-15: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 13-4 for load conditions. TABLE 13-11: I2C BUS START/STOP BITS REQUIREMENTS Parameter No.
PIC16C62B/72A FIGURE 13-16: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 13-4 for load conditions. TABLE 13-12: I2C BUS DATA REQUIREMENTS Param. No. 100* Sym THIGH Characteristic Clock high time Min Max Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.
PIC16C62B/72A TABLE 13-13: A/D CONVERTER CHARACTERISTICS: PIC16C72A-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C72A-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC72A-04 (COMMERCIAL, INDUSTRIAL) Param Sym No. Characteristic Min Typ† Max Units Conditions — — 8-bits bit VREF = VDD = 5.12V, VSS VAIN VREF A01 NR A02 EABS Total Absolute error — — <±1 LSB VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL Integral linearity error — — <±1 LSB VREF = VDD = 5.
PIC16C62B/72A FIGURE 13-17: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (Tosc/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 13-14: A/D CONVERSION REQUIREMENTS Param Sym No. 130 TAD Characteristic A/D clock period Min Typ† Max Unit s PIC16CXX 1.
PIC16C62B/72A 14.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
PIC16C62B/72A NOTES: DS35008C-page 104 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A 15.0 PACKAGING INFORMATION 15.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example MMMMMMMMMMMM XXXXXXXXXXXXXXX AABBCDE 28-Lead CERDIP Windowed PIC16C72A-04/SP 1317HAT Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX AABBCDE PIC16C72A/JW 1317CAT Example 28-Lead SOIC MMMMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXXXX AABBCDE 28-Lead SSOP PIC16C62B-20/SO 1310/SAA Example XXXXXXXXXXXX XXXXXXXXXXXX PIC16C62B 20I/SS025 AABBCDE Legend: MM...M XX...
PIC16C62B/72A 15.2 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) E1 D 2 n 1 E A2 A L c B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 28 .100 .150 .130 MAX MILLIMETERS NOM 28 2.54 3.56 3.81 3.18 3.30 0.38 7.62 7.94 7.09 7.80 34.16 34.67 3.18 3.30 0.20 0.29 1.02 1.33 0.41 0.48 8.13 8.89 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .160 Molded Package Thickness A2 .125 .135 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
PIC16C62B/72A 15.3 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) E1 D W2 2 n 1 W1 E A2 A c L B1 B A1 eB Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Width Window Length *Controlling Parameter JEDEC Equivalent: MO-058 Drawing No.
PIC16C62B/72A 15.4 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E E1 p D B 2 1 n h 45 c A2 A L Units Dimension Limits n p A1 MIN INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MAX MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 MIN Number of Pins Pitch Overall Height A .093 .104 Molded Package Thickness A2 .088 .094 Standoff A1 .004 .
PIC16C62B/72A 15.5 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n A c A2 A1 L Units Dimension Limits n p MIN INCHES NOM 28 .026 .073 .068 .006 .309 .207 .402 .030 .007 4 .013 5 5 MAX MILLIMETERS* NOM MAX 28 0.66 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.38 0 5 10 0 5 10 MIN Number of Pins Pitch Overall Height A .068 .
PIC16C62B/72A NOTES: DS35008C-page 110 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A APPENDIX A: REVISION HISTORY Version Date A 7/98 Revision Description This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234, and the PIC16C7X Data Sheet, DS30390. APPENDIX B: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table B-1.
PIC16C62B/72A APPENDIX C: MIGRATION FROM BASE-LINE TO MID-RANGE DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a mid-range device (i.e., PIC16CXXX). The following are the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). 2.
PIC16C62B/72A INDEX A A/D ..................................................................................... 49 A/D Converter Enable (ADIE Bit) ............................... 14 A/D Converter Flag (ADIF Bit) ............................ 15, 51 A/D Converter Interrupt, Configuring ......................... 51 ADCON0 Register ................................................ 9, 49 ADCON1 Register ........................................10, 49, 50 ADRES Register .............................................
PIC16C62B/72A Instruction Set .................................................................... 67 ADDLW ...................................................................... 69 ADDWF ...................................................................... 69 ANDLW ...................................................................... 69 ANDWF ...................................................................... 69 BCF ............................................................................ 69 BSF ..
PIC16C62B/72A PIR1 Register ............................................................... 9, 15 ADIF Bit ..................................................................... 15 CCP1IF Bit ................................................................. 15 SSPIF Bit ................................................................... 15 TMR1IF Bit ................................................................ 15 TMR2IF Bit ................................................................
PIC16C62B/72A SSP .................................................................................... 39 Enable (SSPIE Bit) .................................................... 14 Flag (SSPIF Bit) ......................................................... 15 RA5/SS/AN4 Pin .......................................................... 6 RC3/SCK/SCL Pin ....................................................... 6 RC4/SDI/SDA Pin ........................................................ 6 RC5/SDO Pin ................
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PIC16C62B/72A PIC16C62B/72A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. Examples PART NO.
PIC16C62B/72A DS35008C-page 120 Preliminary 1913 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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