Datasheet

 1999-2013 Microchip Technology Inc. DS41106C-page 99
PIC16C712/716
PORTC
TRISC Register.......................................................... 12
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bits) ............................ 36
Postscaler, WDT................................................................ 29
Assignment (PSA Bit) .......................................... 14, 29
Block Diagram............................................................ 30
Rate Select (PS2:PS0 Bits) ................................. 14, 29
Switching Between Timer0 and WDT ........................ 30
Power-down Mode. See Sleep
Power-on Reset (POR).............................. 51, 54, 55, 58, 59
Oscillator Start-up Timer (OST) ........................... 51, 55
POR Status (POR
Bit)................................................ 18
Power Control (PCON) Register................................ 58
Power-down (PD
Bit) ........................................... 13, 54
Power-on Reset Circuit, External............................... 55
Power-up Timer (PWRT) ..................................... 51, 55
PWRT Enable (PWRTE
Bit)....................................... 52
Time-out (TO
Bit) ................................................. 13, 54
Time-out Sequence.................................................... 57
Time-out Sequence on Power-up .............................. 60
Timing Diagram.......................................................... 83
Prescaler, Capture............................................................. 40
Prescaler, Timer0............................................................... 29
Assignment (PSA Bit) .......................................... 14, 29
Block Diagram............................................................ 30
Rate Select (PS2:PS0 Bits) ................................. 14, 29
Switching Between Timer0 and WDT ........................ 30
Prescaler, Timer1............................................................... 32
Select (T1CKPS1:T1CKPS0 Bits).............................. 31
Prescaler, Timer2............................................................... 42
Select (T2CKPS1:T2CKPS0 Bits).............................. 36
Product Identification System .......................................... 103
Program Counter
PCL Register........................................................ 11, 19
PCLATH Register .......................................... 11, 19, 62
Reset Conditions........................................................ 58
Program Memory ................................................................. 9
Interrupt Vector ............................................................ 9
Paging.................................................................... 9, 19
Program Memory Map ................................................. 9
Reset Vector ................................................................ 9
Program Verification .......................................................... 65
Programming, Device Instructions..................................... 67
PWM (CCP Module) .......................................................... 42
Block Diagram............................................................ 42
CCPR1H:CCPR1L Registers..................................... 42
Duty Cycle.................................................................. 42
Example Frequencies/Resolutions ............................ 43
Output Diagram.......................................................... 42
Period......................................................................... 42
Set-Up for PWM Operation........................................ 43
TMR2 to PR2 Match ............................................36, 42
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17
Q
Q-Clock.............................................................................. 42
R
RAM. See Data Memory
Reader Response ............................................................ 104
Register File....................................................................... 10
Register File Map............................................................... 10
Reset ............................................................................ 51, 54
Block Diagram............................................................ 56
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR
Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers............................. 59
Reset Conditions for PCON Register ........................ 58
Reset Conditions for Program Counter ..................... 58
Reset Conditions for STATUS Register .................... 58
Timing Diagram ......................................................... 83
WDT Reset. See Watchdog Timer (WDT)
Revision History ................................................................. 95
S
Sleep ................................................................................. 64
Sleep ........................................................................... 51, 54
Software Simulator (MPLAB SIM) ..................................... 70
Special Event Trigger. See Compare
Special Features of the CPU ............................................. 51
Special Function Registers................................................ 11
Speed, Operating ................................................................ 1
Stack.................................................................................. 19
STATUS Register .................................................. 11, 13, 62
C Bit ........................................................................... 13
DC Bit ........................................................................ 13
IRP Bit ....................................................................... 13
PD
Bit .................................................................. 13, 54
RP1:RP0 Bits............................................................. 13
TO
Bit .................................................................. 13, 54
Z Bit ........................................................................... 13
T
T1CON Register .......................................................... 11, 31
T1CKPS1:T1CKPS0 Bits........................................... 31
T1OSCEN Bit ............................................................ 31
T1SYNC
Bit ............................................................... 31
TMR1CS Bit............................................................... 31
TMR1ON Bit .............................................................. 31
T2CON Register .......................................................... 11, 36
T2CKPS1:T2CKPS0 Bits........................................... 36
TMR2ON Bit .............................................................. 36
TOUTPS3:TOUTPS0 Bits ......................................... 36
Timer0 ............................................................................... 29
Block Diagram ........................................................... 29
Clock Source Edge Select (T0SE Bit) ................. 14, 29
Clock Source Select (T0CS Bit) .......................... 14, 29
Overflow Enable (T0IE Bit) ........................................ 15
Overflow Flag (T0IF Bit) ...................................... 15, 62
Overflow Interrupt ................................................ 30, 62
Prescaler. See Prescaler, Timer0
Timing Diagram ......................................................... 84
TMR0 Register .......................................................... 11
Timer1 ............................................................................... 31
Block Diagram ........................................................... 32
Capacitor Selection ................................................... 34
Clock Source Select (TMR1CS Bit)........................... 31
External Clock Input Sync (T1SYNC
Bit) ................... 31
Module On/Off (TMR1ON Bit) ................................... 31
Oscillator.............................................................. 31, 34
Oscillator Enable (T1OSCEN Bit) .............................. 31
Overflow Enable (TMR1IE Bit) .................................. 16
Overflow Flag (TMR1IF Bit)....................................... 17
Overflow Interrupt ................................................ 31, 34
Prescaler. See Prescaler, Timer1
Special Event Trigger (CCP) ............................... 34, 41
T1CON Register .................................................. 11, 31
Timing Diagram ......................................................... 84
TMR1H Register.................................................. 11, 31