Datasheet

PIC16C712/716
DS41106C-page 64  1999-2013 Microchip Technology Inc.
9.13 Power-down Mode (Sleep)
Power-Down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD
bit (STATUS<3>) is cleared, the
TO
(STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
DD or VSS, ensure no external
circuitry is drawing current from the I/O pin, power-
down the A/D and the disable external clocks. Pull all I/
O pins, that are high-impedance inputs, high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
DD or
V
SS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
The MCLR
pin must be at a logic high level (VIHMC).
9.13.1 WAKE-UP FROM SLEEP
The device can wake up from Sleep through one of the
following events:
1. External Reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or some
peripheral interrupts.
External MCLR
Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO
and PD bits
in the STATUS register can be used to determine the
cause of device Reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT Time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from Sleep:
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2. CCP Capture mode interrupt.
3. Special Event Trigger (Timer1 in Asynchronous
mode using an external clock).
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.