Datasheet

 1999-2013 Microchip Technology Inc. DS41106C-page 55
PIC16C712/716
9.4 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
V
DD rise is detected (to a level of 1.5V-2.1V). To take
advantage of the POR, just tie the MCLR
pin directly (or
through a resistor) to V
DD. This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for V
DD is specified
(parameter D004). For a slow rise time, see Figure 9-5.
When the device starts normal operation (exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating conditions are
met. Brown-out Reset may be used to meet the start-
up conditions.
FIGURE 9-5: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD POWER-UP)
9.5 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33), on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows V
DD to rise to an
acceptable level. A Configuration bit is provided to
enable/disable the PWRT.
The power-up time delay will vary from chip to chip due
to V
DD, temperature, and process variation. See DC
parameters for details.
9.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
9.7 Brown-Out Reset (BOR)
The PIC16C712/716 members have on-chip Brown-
out Reset circuitry. A Configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Reset circuitry. If V
DD falls below 4.0V, refer
to V
BOR parameter D005(VBOR) for a time greater than
parameter (T
BOR) in Table 12-6. The brown-out situa-
tion will reset the chip. A Reset is not guaranteed to
occur if VDD falls below 4.0V for less than parameter
(T
BOR).
On any Reset (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in Reset until V
DD rises above
V
BOR. The Power-up Timer will now be invoked and will
keep the chip in Reset an additional 72 ms.
If V
DD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-Up Timer will execute a
72 ms Reset. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-7
shows typical Brown-out situations.
For operations where the desired brown-out voltage is
other than 4V, an external brown-out circuit must be
used. Figure 9-8, 9-9 and 9-10 show examples of
external brown-out protection circuits.
Note 1: External Power-on Reset circuit is
required only if V
DD power-up slope is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100 to 1 k will limit any current
flowing into MCLR
from external capacitor
C in the event of MCLR/
VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
R
V
DD
MCLR
PIC16C7XX
VDD