Datasheet

PIC16C712/716
DS41106C-page 48  1999-2013 Microchip Technology Inc.
8.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the Charge Holding capacitor (C
HOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-4. The source
impedance (R
S) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (V
DD). The
source impedance affects the offset voltage at the
analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 10 k. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, T
ACQ, see
the PIC
®
Mid-Range Reference Manual, (DS33023).
This equation calculates the acquisition time to within
1/2 LSb error (512 steps for the A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified accuracy.
FIGURE 8-4: ANALOG INPUT MODEL
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
CPIN
VA
Rs
ANx
5 pF
V
DD
VT = 0.6V
VT = 0.6V
I leakage
R
IC  1k
Sampling
Switch
SS
R
SS
CHOLD
= DAC capacitance
V
SS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
= 51.2 pF
 500 nA
Legend: CPIN
VT
I leakage
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions