Datasheet

 1999-2013 Microchip Technology Inc. DS41106C-page 25
PIC16C712/716
PORTB pins RB3:RB1 are multiplexed with several
peripheral functions (Table 3-3). PORTB pins RB3:RB0
have Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISB as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
0
1
QD
Q
CK
QD
Q
CK
QD
Q
CK
QD
Q
CK
0
1
0
1
TTL Buffer
TRISB<1>
PORTB<1>
TRISCCP<0>
DATACCP<0>
RB1/T1OSO/T1CKI
RD
Data Bus
WR
WR
WR
WR TRISB
T1OSCEN
RD PORTB
TMR1CS
DATACCP
DATACCP
TRISCCP
PORTB
T1CLKIN
ST
Buffer
P
V
DD
Weak
Pull-up
RBPU
(1)
T1OSCEN
T1CS
VSS
VDD
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
0
1
TMR1CS