Datasheet

 1999-2013 Microchip Technology Inc. DS41106C-page 11
PIC16C712/716
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on
all other
Resets (4)
Bank 0
00h INDF
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
02h PCL
(1)
Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS
(1)
IRP
(4)
RP1
(4)
RP0 TO PD ZDCCrr01 1xxx rr0q quuu
04h FSR
(1)
Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA
(5,6)
— ——
(7)
PORTA Data Latch when written: PORTA pins when read --xx xxxx --xu uuuu
06h PORTB
(5,6)
PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h DATACCP —
(7)
—
(7)
—
(7)
—
(7)
—
(7)
DCCP
—
(7)
DT1CK
xxxx xxxx xxxx xuxu
08h-09h — Unimplemented — —
0Ah PCLATH
(1,2)
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh INTCON
(1)
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
—ADIF— — — CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h-14h
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Dh — Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
—ADON0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’,
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: Other (non Power-up) Resets include: external Reset through MCLR
and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device Reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.