PIC16C712/716 8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM Devices included in this Data Sheet: • PIC16C716 18-pin PDIP, SOIC, Windowed CERDIP • High-performance RISC CPU • Only 35 single-word instructions to learn • All single-cycle instructions except for program branches which are two cycle • Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle Device Program Memory Data Memory PIC16C712 1K 128 PIC16C716 2K 128 • Interrupt capability (up to 7 interna
PIC16C712/716 Key Features PIC® Mid-Range Reference Manual (DS33023) PIC16C712 PIC16C716 Operating Frequency DC – 20 MHz DC – 20 MHz Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) Program Memory (14-bit words) 1K 2K Data Memory (bytes) 128 128 Interrupts 7 7 I/O Ports Ports A,B Ports A,B Timers 3 3 Capture/Compare/PWM modules 1 1 8-bit Analog-to-Digital Module 4 input channels 4 input channels PIC16C7XX FAMILY OF DEVICES Clock Memory PIC16C710 PIC16C71 PIC16C
PIC16C712/716 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 I/O Ports ...................................................................................
PIC16C712/716 NOTES: DS41106C-page 4 1999-2013 Microchip Technology Inc.
PIC16C712/716 1.0 DEVICE OVERVIEW There are two devices (PIC16C712, PIC16C716) covered by this data sheet. This document contains device-specific information. Additional information may be found in the PIC® MidRange Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site.
PIC16C712/716 TABLE 1-1: Pin Name MCLR/VPP MCLR PIC16C712/716 PINOUT DESCRIPTION PIC16C712/716 DIP, SOIC SSOP 4 4 16 Type Type I ST Master clear (Reset) input. This pin is an active low Reset to the device. Programming voltage input I ST I CMOS Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. CMOS otherwise. External clock source input.
PIC16C712/716 TABLE 1-1: PIC16C712/716 PINOUT DESCRIPTION (CONTINUED) Pin Name PIC16C712/716 DIP, SOIC SSOP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT RB0 INT 6 RB1/T1OSO/T1CKI RB1 T1OSO 7 7 I/O I TTL ST Digital I/O External Interrupt I/O O TTL — I ST Digital I/O Timer1 oscillator output. Connects to crystal in oscillator mode. Timer1 external clock input.
PIC16C712/716 NOTES: DS41106C-page 8 1999-2013 Microchip Technology Inc.
PIC16C712/716 2.0 MEMORY ORGANIZATION There are two memory blocks in each of these PIC® microcontroller devices. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur. FIGURE 2-2: PC<12:0> CALL, RETURN RETFIE, RETLW Additional information on device memory may be found in the PIC® Mid-Range Reference Manual, (DS33023). 2.
PIC16C712/716 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1(1) RP0 (STATUS<6:5>) = 00 Bank 0 = 01 Bank 1 = 10 Bank 2 (not implemented) = 11 Bank 3 (not implemented) Note 1: Maintain this bit clear to ensure upward compatibility with future products. Each bank extends up to 7Fh (128 bytes).
PIC16C712/716 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section. The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device.
PIC16C712/716 TABLE 2-1: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: Value on POR, all other BOR Resets (4) Bank 1 80h INDF(1) 81h OPTION_ REG 82h PCL(1) 83h STATUS(1) 84h FSR (1) 85h TRISA 86h TRISB 87h TRISCCP 88h-89h — 8Ah PCLATH(1,2) 8Bh INTCON(1) 8Ch PIE1 8Dh — 8Eh PCON 8Fh-91h 92h 93h-9Eh 9Fh — PR2 Addressing this location uses contents of FSR to address data memory (not a physical register
PIC16C712/716 2.2.2.1 Status Register It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any Status bits, see the “Instruction Set Summary.” The STATUS register, shown in Figure 2-4, contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory.
PIC16C712/716 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. FIGURE 2-5: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16C712/716 2.2.2.3 INTCON Register Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 2-6: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C712/716 2.2.2.4 PIE1 Register Note: This register contains the individual enable bits for the peripheral interrupts. FIGURE 2-7: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16C712/716 2.2.2.5 PIR1 Register Note: This register contains the individual flag bits for the peripheral interrupts. FIGURE 2-8: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C712/716 2.2.2.6 PCON Register Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. These devices contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. FIGURE 2-9: If the BODEN Configuration bit is set, BOR is ‘1’ on Power-on Reset. If the BODEN Configuration bit is clear, BOR is unknown on Power-on Reset.
PIC16C712/716 2.3 PCL and PCLATH The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.
PIC16C712/716 2.5 EXAMPLE 2-2: Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
PIC16C712/716 3.0 I/O PORTS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PIC® Mid-Range Reference Manual, (DS33023). 3.1 PORTA and the TRISA Register PORTA is a 5-bit wide bidirectional port. The corresponding data direction register is TRISA.
PIC16C712/716 FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 DATA BUS D Q VDD VDD WR PORT Q CK P Data Latch D WR TRIS N Q VSS VSS Analog input mode Q CK I/O pin TRIS Latch TTL Input Buffer RD TRIS Q D EN RD PORT To A/D Converter FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN DATA BUS D Q WR PORT CK Q I/O Pin N Data Latch D WR TRIS Q CK VSS VSS Schmitt Trigger Input Buffer Q TRIS Latch RD TRIS Q D ENEN RD PORT TMR0 Clock Input DS41106C-page 22 1999-2013 Microchip Technology Inc.
PIC16C712/716 TABLE 3-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF bit 0 bit 1 bit 2 bit 3 TTL TTL TTL TTL Function Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input or VREF Input/output or external clock input for Timer0 RA4/T0CKI bit 4 ST Output is open drain type Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit
PIC16C712/716 3.2 PORTB and the TRISB Register Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. PORTB is an 8-bit wide bidirectional port. The corresponding data direction register is TRISB.
PIC16C712/716 PORTB pins RB3:RB1 are multiplexed with several peripheral functions (Table 3-3). PORTB pins RB3:RB0 have Schmitt Trigger input buffers. PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTB pin.
PIC16C712/716 FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN VDD RBPU(1) weak P pull-up T1OSCEN VDD PORTB<2> DATA BUS WR PORTB D Q CK RB1/T1OSO/T1CKI Q VSS TRISB<2> D WR TRISB Q CK Q T1OSCEN RD PORTB TTL Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC16C712/716 FIGURE 3-7: BLOCK DIAGRAM OF RB7:RB4 PINS VDD RBPU(1) DATA BUS weak P pull-up VDD Data Latch D Q WR PORT I/O pin CK TRIS Latch D Q WR TRIS VSS TTL Buffer CK ST Buffer RD TRIS Q Latch D EN RD PORT Q1 Set RBIF Q From other RB7:RB4 pins D RD PORT EN Q3 RB7:RB6 in Serial Programming mode Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC16C712/716 TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB 1111 1111 1111 1111 81h OPTION_REG 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C712/716 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the PIC® Mid-Range Reference Manual, (DS33023). The Timer0 module timer/counter has the following features: • • • • • • 4.
PIC16C712/716 4.2.1 SWITCHING PRESCALER ASSIGNMENT 4.3 The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep since the timer is shut off during Sleep.
PIC16C712/716 5.0 TIMER1 MODULE 5.1 The Timer1 module timer/counter has the following features: • 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) • Readable and writable (Both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • Reset from CCP module trigger Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).
PIC16C712/716 FIGURE 5-2: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1H Synchronized clock input 0 TMR1 TMR1L 1 TMR1ON on/off T1SYNC T1OSC RB1/T1OSO/T1CKI RB2/T1OSI 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Synchronize Prescaler 1, 2, 4, 8 det 0 2 T1CKPS1:T1CKPS0 TMR1CS Sleep input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 5.
PIC16C712/716 TABLE 5-1: TMR1 Module Mode Off TMR1 MODULE AND PORTB OPERATION Clock Source Control Bits N/A T1CON = --xx 0x00 FOSC/4 T1CON = --xx 0x01 TMR1 Module Operation Off TMR1 module uses the main oscillator as clock source. TMR1ON can turn on or turn off Timer1. Counter External circuit T1CON = --xx 0x11 TMR1 module uses the external TR1SCCP = ---- -x-1 signal on the RB1/T1OSO/ T1CKI pin as a clock source. TMR1ON can turn on or turn off Timer1.
PIC16C712/716 5.3 Timer1 Oscillator 5.4 Timer1 Interrupt A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. Table 5-2 shows the capacitor selection for the Timer1 oscillator.
PIC16C712/716 NOTES: 1999-2013 Microchip Technology Inc.
PIC16C712/716 6.0 TIMER2 MODULE Timer2 has a control register, shown in Figure 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption.
PIC16C712/716 6.1 Timer2 Operation 6.2 Timer2 can be used as the PWM time base for PWM mode of the CCP module. Timer2 Interrupt The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The TMR2 register is readable and writable, and is cleared on any device Reset.
PIC16C712/716 NOTES: DS41106C-page 38 1999-2013 Microchip Technology Inc.
PIC16C712/716 7.0 CAPTURE/COMPARE/PWM (CCP) MODULE(S) Additional information on the CCP module is available in the PIC® Mid-Range Reference Manual, (DS33023). Each CCP (Capture/Compare/PWM) module contains a 16-bit register, which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes.
PIC16C712/716 7.1 7.1.4 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software.
PIC16C712/716 7.2 7.2.1 Compare Mode The user must configure the RB3/CCP1 pin as the CCP output by clearing the TRISCCP<2> bit. In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RB3/CCP1 pin is either: Note: • driven High • driven Low • remains Unchanged 7.2.2 The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. FIGURE 7-4: 7.
PIC16C712/716 7.3 7.3.1 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISCCP<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is neither the PORTB I/O data latch nor the DATACCP latch. Figure 7-5 shows a simplified block diagram of the CCP module in PWM mode.
PIC16C712/716 7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISCCP<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
PIC16C712/716 7.4 CCP1 Module and PORTB Operation When the CCP module is disabled, PORTB<3> operates as a normal I/O pin. When the CCP module is enabled, PORTB<3> operation is affected. Multiplexing details of the CCP1 module are shown on PORTB<3>, refer to Figure 3.6. Table 7-5 below shows the effects of the CCP module operation on PORTB<3> TABLE 7-5: CCP1 Module Mode Off Capture Compare PWM .
PIC16C712/716 8.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE Additional information on the A/D module is available in the PIC® Mid-Range Reference Manual, (DS33023). The Analog-to-Digital (A/D) Converter module has four inputs. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation.
PIC16C712/716 FIGURE 8-2: U-0 — bit7 ADCON1 REGISTER (ADDRESS 9Fh) U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7-3: Unimplemented: Read as ‘0’ bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 0x0 0x1 100 101 11x RA0 A A A A D RA1 A A A A D RA2 A A D D D RA3 A VREF A VREF D VREF VDD RA3 VDD RA3 VDD A = Analog input D = Digital I/O DS41106C-page 46 1999
PIC16C712/716 The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared and the A/D Interrupt Flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 8-3. 1. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. 2.
PIC16C712/716 8.1 A/D Acquisition Requirements To calculate the minimum acquisition time, TACQ, see the PIC® Mid-Range Reference Manual, (DS33023). This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. For the A/D converter to meet its specified accuracy, the Charge Holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level.
PIC16C712/716 8.2 Selecting the A/D Conversion Clock 8.3 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s.
PIC16C712/716 8.4 Note: 8.5 A/D Conversions GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “Special Event Trigger” sets the GO/ DONE bit (starts a conversion).
PIC16C712/716 9.0 SPECIAL FEATURES OF THE CPU The PIC16C712/716 devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection.
PIC16C712/716 FIGURE 9-1: CP1 CP0 CONFIGURATION WORD CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE bit13 WDTE FOSC1 FOSC0 bit0 Register:CONFIG Address2007h bit 13-8, 5-4: CP1:CP0: Code Protection bits (2) Code Protection for 2K Program memory (PIC16C716) 11 = Programming code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected bit 13-8, 5-4: Code Protection for 1K Program memory bits (PIC16C712) 11 = Programming code protection off 10 = Prog
PIC16C712/716 9.2 TABLE 9-1: Oscillator Configurations 9.2.1 Ranges Tested: OSCILLATOR TYPES The PIC16CXXX can be operated in four different Oscillator modes. The user can program two Configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC 9.2.2 In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 9-2). The PIC16CXXX oscillator design requires the use of a parallel cut crystal.
PIC16C712/716 9.2.3 RC OSCILLATOR 9.3 For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation.
PIC16C712/716 9.4 Power-On Reset (POR) 9.5 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when VDD rise is detected (to a level of 1.5V-2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified (parameter D004). For a slow rise time, see Figure 9-5.
PIC16C712/716 FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset S BODEN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter PWRT See Table 9-3 for time-out BODEN situations. Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
PIC16C712/716 FIGURE 9-8: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD FIGURE 9-10: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 VDD VDD 33k MCP809 Q1 10k Vss MCLR 40k bypass capacitor VDD VDD RST PIC16C7XX MCLR PIC16C7XX Note 1: This circuit will activate Reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit.
PIC16C712/716 9.9 Power Control/Status Register (PCON) The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (the BODEN Configuration bit is clear). BOR must then be set by the user and checked on subsequent Resets to see if it is clear, indicating a brown-out has occurred. The Power Control/Status Register, PCON has two bits. Bit 0 is Brown-out Reset Status bit, BOR. If the BODEN Configuration bit is set, BOR is ‘1’ on Power-on Reset.
PIC16C712/716 TABLE 9-6: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16C712/716 Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA(4) --0x 0000 --xx xxxx --xu uuuu PORTB(5) xxxx xxxx uuuu uuuu uuuu uuuu DATACCP ---- -x-x ---- -u-u ---- -
PIC16C712/716 FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS41106C-page 60 1999-2013 Microchip Techn
PIC16C712/716 9.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The PIC16C712/716 devices have up to 7 sources of interrupt. The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2.
PIC16C712/716 9.10.1 INT INTERRUPT 9.11 External interrupt on RB0/INT pin is edge triggered, either rising if bit INTEDG (OPTION_REG<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16C712/716 9.12 Watchdog Timer (WDT) The Watchdog Timer is as a free running, on-chip, RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device have been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT Time-out generates a device Reset (Watchdog Timer Reset).
PIC16C712/716 9.13 Power-down Mode (Sleep) Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or high-impedance).
PIC16C712/716 When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction.
PIC16C712/716 9.16 In-Circuit Serial Programming™ PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
PIC16C712/716 10.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXXX instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 10-1 shows the opcode field descriptions.
PIC16C712/716 TABLE 10-2: Mnemonic, Operands PIC16CXXX INSTRUCTION SET Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move
PIC16C712/716 11.
PIC16C712/716 11.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC16C712/716 11.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16C712/716 11.11 PICSTART Plus Development Programmer 11.12 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC16C712/716 12.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.
PIC16C712/716 FIGURE 12-1: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +125°C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 20 10 4 40 30 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC16LC712/716 VOLTAGE-FREQUENCY GRAPH, 0°C < TA < +70°C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16C712/716 12.1 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) +70°C for commercial Operating temperature 0°C TA +85°C for industrial -40°C TA -40°C TA +125°C for extended DC CHARACTERISTICS Param No. D001 D001A Sym. VDD Characteristic Supply Voltage Min. Typ† Max. Units 4.0 4.5 VBOR* — — — 5.5 5.5 5.
PIC16C712/716 12.2 DC Characteristics: PIC16LC712/716-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial +85°C for industrial -40°C TA DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units 2.5 VBOR* — — 5.5 5.5 V V Conditions D001 VDD Supply Voltage D002* VDR RAM Data Retention Voltage(1) — 1.
PIC16C712/716 12.3 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712716-20 (Commercial, Industrial, Extended) PIC16LC712/716-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Sym.
PIC16C712/716 DC CHARACTERISTICS Param No. D080 Sym.
PIC16C712/716 12.4 12.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low 1999-2013 Microchip Technology Inc.
PIC16C712/716 12.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 12-1 apply to all timing specifications, unless otherwise noted. Figure 12-3 specifies the load conditions for the timing specifications.
PIC16C712/716 12.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 12-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 12-2: Param No. 1A Sym. FOSC EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic Min. External CLKIN Frequency (Note 1) DC — 4 MHz RC and XT osc modes DC — 4 MHz HS osc mode (-04) Oscillator Frequency (Note 1) 1 TOSC External CLKIN Period (Note 1) Oscillator Period (Note 1) Typ† Max.
PIC16C712/716 FIGURE 12-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 12-3 for load conditions. TABLE 12-3: Param No. 10* CLKOUT AND I/O TIMING REQUIREMENTS Sym. Characteristic TosH2ckL OSC1 to CLKOUT Min. Typ† Max.
PIC16C712/716 FIGURE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 12-3 for load conditions. FIGURE 12-7: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym. Characteristic Min. Typ† Max.
PIC16C712/716 FIGURE 12-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 12-3 for load conditions. TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym. Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * † Tt0L Min. Typ† Max. Units Conditions 0.
PIC16C712/716 FIGURE 12-9: CAPTURE/COMPARE/PWM TIMINGS CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 12-3 for load conditions. TABLE 12-6: CAPTURE/COMPARE/PWM REQUIREMENTS Param No. Sym.
PIC16C712/716 TABLE 12-7: A/D CONVERTER CHARACTERISTICS: PIC16C712/716-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C712/716-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC712/716-04 (COMMERCIAL, INDUSTRIAL) Param Sym. Characteristic No. A01 A02 NR Resolution EABS Total Absolute error Min. Typ† Max. Units Conditions — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF VREF = VDD = 5.12V, VSS £ VAIN £ VREF A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.
PIC16C712/716 FIGURE 12-10: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 Tcy (TOSC/2) (1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 12-8: A/D CONVERSION REQUIREMENTS Param Sym. Characteristic No. 130 TAD A/D clock period Standard Min. Typ† Max.
PIC16C712/716 NOTES: DS41106C-page 88 1999-2013 Microchip Technology Inc.
PIC16C712/716 13.0 PACKAGING INFORMATION 13.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead CERDIP Windowed PIC16C716-04/P 0510017 Example XXXXXXXX XXXXXXXX YYWWNNN 18-Lead SOIC (.300”) PIC16C 716/JW 0510017 Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC16C712-20 /SO 0510017 YYWWNNN 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16C712 -20I/SS 0510017 Legend: XX...
PIC16C712/716 13.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.
PIC16C712/716 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C712/716 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D W2 2 n 1 W1 E A2 A c L A1 eB B1 p B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC16C712/716 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C712/716 NOTES: DS41106C-page 94 1999-2013 Microchip Technology Inc.
PIC16C712/716 APPENDIX A: REVISION HISTORY Version Date Revision Description A 2/99 This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234, and the PIC16C7X Data Sheet, DS30390. B 9/05 Removed Preliminary Status. C 1/13 Added a note to each package outline drawing. APPENDIX B: CONVERSION CONSIDERATIONS There are no previous versions of this device.
PIC16C712/716 NOTES: DS41106C-page 96 1999-2013 Microchip Technology Inc.
PIC16C712/716 INDEX A A/D ..................................................................................... 45 A/D Converter Enable (ADIE Bit) ............................... 16 A/D Converter Flag (ADIF Bit) ............................. 17, 47 A/D Converter Interrupt, Configuring ......................... 47 ADCON0 Register................................................ 11, 45 ADCON1 Register.......................................... 12, 45, 46 ADRES Register ..........................................
PIC16C712/716 Interrupt Sources.......................................................... 51, 61 A/D Conversion Complete ......................................... 47 Block Diagram............................................................. 61 Capture Complete (CCP) ............................................ 40 Compare Complete (CCP) ......................................... 41 Interrupt-on-Change (RB7:RB4 ) ............................... 24 RB0/INT Pin, External .........................................
PIC16C712/716 PORTC TRISC Register.......................................................... 12 Postscaler, Timer2 Select (TOUTPS3:TOUTPS0 Bits) ............................ 36 Postscaler, WDT ................................................................ 29 Assignment (PSA Bit) .......................................... 14, 29 Block Diagram............................................................ 30 Rate Select (PS2:PS0 Bits) ................................. 14, 29 Switching Between Timer0 and WDT ..
PIC16C712/716 TMR1L Register ................................................... 11, 31 Timer2 Block Diagram............................................................ 36 Postscaler. See Postscaler, Timer2 PR2 Register .................................................. 12, 36, 42 Prescaler. See Prescaler, Timer2 T2CON Register .................................................. 11, 36 TMR2 Register ..................................................... 11, 36 TMR2 to PR2 Match Enable (TMR2IE Bit) ...........
PIC16C712/716 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16C712/716 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16C712/716 PIC16C712/716 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X -XX Frequency Temperature Range Range /XX XXX Package Pattern Examples: a) b) Device: PIC16C712(1), PIC16C712T(2);VDD range 4.0V to 5.5V PIC16LC712(1), PIC16LC712T(2);VDD range 2.5V to 5.5V PIC16C716(1), PIC16C716T(2);VDD range 4.0V to 5.5V PIC16LC716(1), PIC16LC716T(2);VDD range 2.5V to 5.
PIC16C712/716 NOTES: 1999-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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