Datasheet

PIC16C71X
DS30272A-page 40  1997 Microchip Technology Inc.
7.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-5. The source
impedance (R
S) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor C
HOLD. The sampling switch (RSS)
impedance varies over the device voltage (V
DD),
Figure 7-5. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, Equation 7-
1 may be used. This equation calculates the acquisition
time to within 1/2 LSb error is used (512 steps for the
A/D). The 1/2 LSb error is the maximum error allowed
for the A/D to meet its specified accuracy.
EQUATION 7-1: A/D MINIMUM CHARGING
TIME
VHOLD = (VREF - (VREF/512)) • (1 - e
(-TCAP/CHOLD(RIC + RSS + RS))
)
Given: VHOLD = (VREF/512), for 1/2 LSb resolution
The above equation reduces to:
TCAP = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
Example 7-1 shows the calculation of the minimum
required acquisition time T
ACQ. This calculation is
based on the following system assumptions.
C
HOLD = 51.2 pF
Rs = 10 k
Ω
1/2 LSb error
V
DD = 5V → Rss = 7 kΩ
Temp (application system max.) = 50°C
V
HOLD = 0 @ t = 0
EXAMPLE 7-1: CALCULATING THE
MINIMUM REQUIRED
AQUISITION TIME
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
T
ACQ = 5 µs + TCAP + [(Temp - 25°C)(0.05 µs/°C)]
T
CAP = -CHOLD (RIC + RSS + RS) ln(1/511)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
-0.921 µs (-6.2364)
5.747 µs
T
ACQ = 5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]
10.747 µs + 1.25 µs
11.997 µs
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
Note 2: The charge holding capacitor (C
HOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specifi-
cation.
Note 4: After a conversion has completed, a
2.0T
AD delay must complete before acqui-
sition can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
FIGURE 7-5: ANALOG INPUT MODEL
CPIN
VA
Rs
ANx
5 pF
V
DD
VT = 0.6V
V
T = 0.6V
I leakage
R
IC ≤ 1k
Sampling
Switch
SS
R
SS
CHOLD
= DAC capacitance
V
SS
6V
Sampling Switch
5V
4V
3V
2V
5 6 7 8 9 10 11
( kΩ )
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions