Datasheet

PIC16C71X
DS30272A-page 146  1997 Microchip Technology Inc.
Applicable Devices 710 71 711 715
FIGURE 15-6: A/D CONVERSION TIMING
TABLE 15-7: A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
130 T
AD A/D clock period
PIC16C71
2.0 — — µs TOSC based, VREF ≥ 3.0V
PIC16LC71
2.0 — — µs TOSC based, VREF full range
PIC16C71 2.0 4.0 6.0 µs A/D RC Mode
PIC16LC71 3.0 6.0 9.0 µs A/D RC Mode
131 TCNV Conversion time
(not including S/H time) (Note 1)
— 9.5 — TAD
132 TACQ Acquisition time Note 2
5*
20
—
—
—
µs
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than
1 LSb (i.e., 19.5 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134 TGO Q4 to A/D clock start — Tosc/2§ — — If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 TSWC Switching from convert → sample time 1.5§ — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ These specifications ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(T
OSC/2)
(1)
7 6 5 4 3 2 1 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 Tcy