Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 18 8-Bit 4 MHz I/O number 13



1997 Microchip Technology Inc. DS30272A-page 1

PIC16C71X

8-Bit CMOS Microcontrollers with A/D Converter

Devices included in this data sheet:

• PIC16C710

• PIC16C71

• PIC16C711

• PIC16C715

PIC16C71X Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Up to 2K x 14 words of Program Memory,

up to 128 x 8 bytes of Data Memory (RAM)

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM

technology

• Fully static design

• Wide operating voltage range: 2.5V to 6.0V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temperature

ranges

• Program Memory Parity Error Checking Circuitry

with Parity Error Reset (PER) (PIC16C715)

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

- 15

A typical @ 3V, 32 kHz

- < 1

A typical standby current

PIC16C71X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• 8-bit multichannel analog-to-digital converter

• Brown-out detection circuitry for

Brown-out Reset (BOR)

• 13 I/O Pins with Individual Direction Control

Pin Diagrams

PIC16C7X Features 710 71 711 715

Program Memory (EPROM)

x 14

512 1K 1K 2K

Data Memory (Bytes) x 8 36 36 68 128

I/O Pins 13 13 13 13

Timer Modules 1 1 1 1

A/D Channels 4 4 4 4

In-Circuit Serial Programming Yes Yes Yes Yes

Brown-out Reset Yes — Yes Yes

Interrupt Sources 4 4 4 4

RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

MCLR/VPP

VSS

RB0/INT

RB1

RB2

RB3

RA1/AN1

RA0/AN0

OSC1/CLKIN

OSC2/CLKOUT

RB7

RB6

RB5

RB4

• 1

VDD

SSOP

RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

MCLR/VPP

VSS

RB0/INT

RB1

RB2

RB3

RA1/AN1

RA0/AN0

OSC1/CLKIN

OSC2/CLKOUT

RB7

RB6

RB5

RB4

• 1

PIC16C710

PDIP, SOIC, Windowed CERDIP

PIC16C71

PIC16C711

PIC16C715

PIC16C710

PIC16C711

PIC16C715

Summary of content (177 pages)

PAGE 1
PIC16C71X 8-Bit CMOS Microcontrollers with A/D Converter Devices included in this data sheet: PIC16C71X Peripheral Features: • • • • • Timer0: 8-bit timer/counter with 8-bit prescaler • 8-bit multichannel analog-to-digital converter • Brown-out detection circuitry for Brown-out Reset (BOR) • 13 I/O Pins with Individual Direction Control PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C71X Microcontroller Core Features: 710 71 711 715 Program Memory (EPROM) x 14 512 1K 1K 2K Data Memory (Bytes) x 8
PAGE 2
PIC16C71X Table of Contents 1.0 General Description .................................................................................................................................................................... 3 2.0 PIC16C71X Device Varieties...................................................................................................................................................... 5 3.0 Architectural Overview....................................................................................
PAGE 3
PIC16C71X 1.0 GENERAL DESCRIPTION The PIC16C71X is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PAGE 4
PIC16C71X TABLE 1-1: PIC16C71X FAMILY OF DEVICES PIC16C710 Clock Memory Memory PIC16C72 PIC16CR72(1) 20 20 20 20 20 EPROM Program Memory (x14 words) 512 1K 1K 2K 2K — ROM Program Memory (14K words) — — — — — 2K Data Memory (bytes) 36 36 68 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 — — — — 1 1 Serial Port(s) (SPI/I2C, USART) — — — — SPI/I2C SPI/I2C Parallel Slave Port — — — — — — A/D Converter (8-bit) Channels
PAGE 5
PIC16C71X 2.0 PIC16C71X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C71X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C71X family, there are two device “types” as indicated in the device number: 1. 2. 2.
PAGE 6
PIC16C71X NOTES: DS30272A-page 6  1997 Microchip Technology Inc.
PAGE 7
PIC16C71X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus.
PAGE 8
PIC16C71X FIGURE 3-1: Device PIC16C71X BLOCK DIAGRAM Program Memory Data Memory (RAM) PIC16C710 PIC16C71 PIC16C711 PIC16C715 512 x 14 1K x 14 1K x 14 2K x 14 36 x 8 36 x 8 68 x 8 128 x 8 13 8 Data Bus Program Counter PORTA EPROM Program Memory Program Bus RAM File Registers 8 Level Stack (13-bit) 14 RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RAM Addr (1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg RB0/INT RB7:RB1 STATUS reg 8 3 MUX Power-up Timer Ins
PAGE 9
PIC16C71X TABLE 3-1: Pin Name PIC16C710/71/711/715 PINOUT DESCRIPTION DIP SSOP Pin# Pin#(4) SOIC Pin# I/O/P Type Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. 4 4 4 I/P ST Master clear (reset) input or programming voltage input.
PAGE 10
PIC16C71X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.
PAGE 11
PIC16C71X 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C71X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space.
PAGE 12
PIC16C71X 4.2 Data Memory Organization The data memory is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit. RP0 (STATUS<5>) = 1 → Bank 1 RP0 (STATUS<5>) = 0 → Bank 0 Each Bank extends up to 7Fh (128 bytes). The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM.
PAGE 13
PIC16C71X FIGURE 4-5: PIC16C711 REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB ADCON0 ADRES INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCON ADCON1 ADRES PCLATH INTCON PCLATH INTCON General Purpose Register General Purpose Register 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch Mapped in Bank 0(2) 4Fh CFh 50h D0h 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'.
PAGE 14
PIC16C71X 4.2.2 The special function registers can be classified into two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature. SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device.
PAGE 15
PIC16C71X TABLE 4-2: Address Name PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR, PER Value on all other resets (3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB IRP(4) RP1(
PAGE 16
PIC16C71X TABLE 4-2: Address Name PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PAGE 17
PIC16C71X 4.2.2.1 STATUS REGISTER Applicable Devices 710 71 711 715 The STATUS register, shown in Figure 4-7, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PAGE 18
PIC16C71X 4.2.2.2 OPTION REGISTER Applicable Devices Note: 710 71 711 715 The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-8: R/W-1 RBPU bit7 To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer by setting bit PSA (OPTION<3>).
PAGE 19
PIC16C71X 4.2.2.3 INTCON REGISTER Applicable Devices Note: 710 71 711 715 The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 4-9: R/W-0 GIE bit7 Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PAGE 20
PIC16C71X 4.2.2.4 PIE1 REGISTER Applicable Devices Note: 710 71 711 715 Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the Peripheral interrupts.
PAGE 21
PIC16C71X 4.2.2.5 PIR1 REGISTER Applicable Devices Note: 710 71 711 715 This register contains the individual flag bits for the Peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PAGE 22
PIC16C71X 4.2.2.6 PCON REGISTER Applicable Devices Note: 710 71 711 715 The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset (BOR) condition from a Power-on Reset condition. For the PIC16C715 the PCON register also contains status bits MPEEN and PER.
PAGE 23
PIC16C71X 4.3 PCL and PCLATH 4.3.2 The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-14 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PAGE 24
PIC16C71X 4.5 Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used). EXAMPLE 4-1: ORG 0x500 BSF PCLATH,3 BCF PCLATH,4 CALL SUB1_P1 : : : ORG 0x900 SUB1_P1: : : RETURN Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.
PAGE 25
PIC16C71X 5.0 I/O PORTS Applicable Devices FIGURE 5-1: 710 71 711 715 Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 BLOCK DIAGRAM OF RA3:RA0 PINS Data bus D Q VDD WR Port Q CK Data Latch PORTA is a 5-bit latch. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output.
PAGE 26
PIC16C71X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST Function Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input/VREF Input/output or external clock input for Timer0 Output is open drain type Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address Name 05h Bit 7 Bit 6 Bit 5 Bit 4
PAGE 27
PIC16C71X 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).
PAGE 28
PIC16C71X FIGURE 5-4: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C71) FIGURE 5-5: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C710/711/715) VDD RBPU(2) VDD weak P pull-up Data Latch D Q Data bus WR Port RBPU(2) Data bus I/O pin(1) CK WR Port TRIS Latch D Q WR TRIS weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q TTL Input Buffer CK RD TRIS Q WR TRIS ST Buffer RD TRIS Latch D Q EN RD Port TTL Input Buffer CK Latch D EN RD Port Set RBIF ST Buffer Q1 Set RBIF From other RB7:RB4 pins
PAGE 29
PIC16C71X TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB 1111 1111 1111 1111 81h, 181h OPTION 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PAGE 30
PIC16C71X 5.3 I/O Programming Considerations 5.3.1 BI-DIRECTIONAL I/O PORTS EXAMPLE 5-3: Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PAGE 31
PIC16C71X 6.0 TIMER0 MODULE Applicable Devices bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. 710 71 711 715 The Timer0 module timer/counter has the following features: • • • • • • The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module.
PAGE 32
PIC16C71X FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0,W PC+3 Instruction Execute PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 PC+6 NT0+1 NT0 Write TMR0 executed FIGURE 6-4: PC+4 MOVF TMR0,W T0+1 T0 TMR0 PC+2 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 re
PAGE 33
PIC16C71X 6.2 Using Timer0 with an External Clock caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns.
PAGE 34
PIC16C71X 6.3 Prescaler When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6).
PAGE 35
PIC16C71X 6.3.1 SWITCHING PRESCALER ASSIGNMENT Note: The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. EXAMPLE 6-1: BCF CLRF BSF CLRWDT MOVLW MOVWF BCF To avoid an unintended device RESET, the following instruction sequence (shown in Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
PAGE 36
PIC16C71X NOTES: DS30272A-page 36  1997 Microchip Technology Inc.
PAGE 37
PIC16C71X 7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE Applicable Devices The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. 710 71 711 715 The A/D module has three registers. These registers are: The analog-to-digital (A/D) converter module has four analog inputs.
PAGE 38
PIC16C71X FIGURE 7-2: ADCON0 REGISTER (ADDRESS 1Fh), PIC16C715 R/W-0 R/W-0 ADCS1 ADCS0 bit7 R/W-0 — R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 — R/W-0 ADON bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) bit 5: Unused bit 6-3: CHS1:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA
PAGE 39
PIC16C71X 2. The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 7-4. 3. 4. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PAGE 40
PIC16C71X 7.1 A/D Acquisition Requirements Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 7-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD.
PAGE 41
PIC16C71X 7.2 Selecting the A/D Conversion Clock 7.3 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input).
PAGE 42
PIC16C71X 7.4 A/D Conversions Example 7-2 shows how to perform an A/D conversion. The RA pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the RA0 pin (channel 0). EXAMPLE 7-2: BSF CLRF BCF MOVLW MOVWF BSF BSF ; ; ; ; Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
PAGE 43
PIC16C71X 7.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF Not all applications require a result with 8-bits of resolution, but may instead require a faster conversion time. The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same.
PAGE 44
PIC16C71X 7.5 A/D Operation During Sleep The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and the result loaded into the ADRES register.
PAGE 45
PIC16C71X 7.9 Transfer Function FIGURE 7-6: A/D TRANSFER FUNCTION The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) is Analog VREF/256 (Figure 7-6). References Digital code output 7.10 A very good reference for understanding A/D converters is the "Analog-Digital Conversion Handbook" third edition, published by Prentice Hall (ISBN 0-13-032848-0).
PAGE 46
PIC16C71X TABLE 7-3: Address REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C710/71/711 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu 0Bh,8Bh INTCON 89h ADRES A/D Result Register 08h ADCON0 ADCS1 ADCS0 — CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000 88h ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00 05h PORTA — — — RA4 R
PAGE 47
PIC16C71X 8.0 SPECIAL FEATURES OF THE CPU Applicable Devices fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. 710 71 711 715 SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt.
PAGE 48
PIC16C71X FIGURE 8-2: CP0 CP0 CONFIGURATION WORD, PIC16C710/711 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 bit13 PWRTE WDTE FOSC1 FOSC0 bit0 Register: Address CONFIG 2007h bit 13-7 CP0: Code protection bits (2) 5-4: 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT
PAGE 49
PIC16C71X 8.2 Oscillator Configurations 8.2.1 OSCILLATOR TYPES TABLE 8-1: The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC 8.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor Ranges Tested: Mode XT CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.
PAGE 50
PIC16C71X TABLE 8-3: CERAMIC RESONATORS, PIC16C710/711/715 TABLE 8-4: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR, PIC16C710/711/715 Ranges Tested: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz HS OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF These values are for design guidance only. See notes at bottom of page. Osc Type Crystal Freq Cap. Range C1 Cap.
PAGE 51
PIC16C71X 8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 8-6 shows implementation of a parallel resonant oscillator circuit.
PAGE 52
PIC16C71X 8.3 Reset Applicable Devices 710 71 711 715 The PIC16CXX differentiates between various kinds of reset: • • • • • • Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (normal operation) Brown-out Reset (BOR) (PIC16C710/711/715) Parity Error Reset (PIC16C715) A simplified block diagram of the on-chip reset circuit is shown in Figure 8-9.
PAGE 53
PIC16C71X 8.4 8.4.1 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST), and Brown-out Reset (BOR) The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. POWER-ON RESET (POR) Applicable Devices Applicable Devices 710 71 711 715 A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V).
PAGE 54
PIC16C71X 8.4.5 TIME-OUT SEQUENCE Applicable Devices 710 71 711 715 On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 8-11, Figure 8-12, and Figure 8-13 depict time-out sequences on power-up.
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PIC16C71X TABLE 8-7: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C71 TO PD 1 0 x 0 0 u 1 1 x 0 1 0 u 0 TABLE 8-8: Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP STATUS BITS AND THEIR SIGNIFICANCE, PIC16C710/711 POR BOR TO PD 0 0 0 1 1 1 1 1 x x x 0 1 1 1 1 1 0 x x 0 0 u 1 1 x 0 x 1 0 u 0 TABLE 8-9: Power-on Reset Illegal, TO is set on POR Illegal, PD is set on P
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PIC16C71X TABLE 8-10: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C710/71/711 Condition Program Counter STATUS Register PCON Register PIC16C710/711 Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset (PIC16C710/711) 000h 0001 1uuu ---- --u0 uuu1 0uuu ---- --uu Interrupt wake-up from SLEEP (1)
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PIC16C71X TABLE 8-12: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C710/71/711 Power-on Reset, Brown-out Reset(5) MCLR Resets WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA ---x 0000 ---u 0000 ---u uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCO
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PIC16C71X TABLE 8-13: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C715 Power-on Reset, Brown-out Reset Parity Error Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA ---x 0000 ---u 0000 ---u uuuu W PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 --
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PIC16C71X FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  1997 Microchip Technology Inc.
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PIC16C71X FIGURE 8-14: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 8-15: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD D VDD 33k VDD 10k R R1 40k MCLR C MCLR PIC16CXX PIC16CXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that voltage drop across R does not violate the device’s electrical specification.
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PIC16C71X 8.5 Interrupts Applicable Devices 710 71 711 715 The PIC16C71X family has 4 sources of interrupt. Interrupt Sources External interrupt RB0/INT TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) A/D Interrupt For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 8-19). The latency is the same for one or two cycle instructions.
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PIC16C71X FIGURE 8-17: INTERRUPT LOGIC, PIC16C710, 71, 711 Wakeup (If in SLEEP mode) T0IF T0IE INTF INTE Interrupt to CPU RBIF RBIE ADIF ADIE GIE FIGURE 8-18: INTERRUPT LOGIC, PIC16C715 T0IF T0IE INTF INTE Wakeup (If in SLEEP mode) Interrupt to CPU RBIF RBIE ADIF ADIE ADIF GIE DS30272A-page 62  1997 Microchip Technology Inc.
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PIC16C71X 8.5.1 8.5.2 INT INTERRUPT TMR0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 6.0) External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set.
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PIC16C71X 8.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 8-1 stores and restores the STATUS and W registers. The user register, STATUS_TEMP, must be defined in bank 0. The example: a) b) c) d) e) Stores the W register. Stores the STATUS register in bank 0. Executes the ISR code.
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PIC16C71X 8.7 Watchdog Timer (WDT) Applicable Devices assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. 710 71 711 715 The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components.
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PIC16C71X 8.8 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).
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PIC16C71X FIGURE 8-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 8.9 PC+1 PC+2 Inst(PC + 2) SLEEP Inst(PC + 1) 8.
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PIC16C71X NOTES: DS30272A-page 68  1997 Microchip Technology Inc.
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PIC16C71X 9.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator.
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PIC16C71X TABLE 9-2: PIC16CXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to
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PIC16C71X 9.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [label] ADDLW Syntax: [label] ANDLW Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) C, DC, Z Status Affected: Z Status Affected: Encoding: 11 k 111x kkkk kkkk Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
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PIC16C71X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [label] BCF Syntax: [label] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
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PIC16C71X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding: Description: 01 1 Cycles: 1(2) If Skip: Example bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is executed.
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PIC16C71X CLRF Clear f Syntax: [label] CLRF Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1→Z Status Affected: Z Encoding: 00 f 0001 1fff ffff CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1→Z Status Affected: Z Encoding: 00 0001 0xxx xxxx Description: The contents of register 'f' are cleared and the Z bit is set. Description: W register is cleared. Zero bit (Z) is set.
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PIC16C71X COMF Complement f Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding: 00 f,d 1001 dfff ffff Description: The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
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PIC16C71X GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 2047 Operands: Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest) None Status Affected: Z Status Affected: Encoding: 10 GOTO k 1kkk kkkk kkkk Encoding: 00 INCF f,d 1010 dfff ffff Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>.
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PIC16C71X INCFSZ Increment f, Skip if 0 IORLW Inclusive OR Literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f) + 1 → (dest), skip if result = 0 (W) .OR. k → (W) Operation: Status Affected: Z Status Affected: None Encoding: Encoding: Description: 00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
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PIC16C71X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. (f) → (dest) Operation: k → (W) Status Affected: Z Status Affected: None Encoding: IORWF 00 f,d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
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PIC16C71X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS → PC, 1 → GIE Status Affected: None Encoding: 00 NOP 0000 0xx0 0000 RETFIE Description: No operation. Encoding: Words: 1 Description: Cycles: 1 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
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PIC16C71X RETLW Return with Literal in W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: TOS → PC Status Affected: None Status Affected: None Encoding: RETLW k 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
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PIC16C71X RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: RLF 00 RRF f,d 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register.
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PIC16C71X SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD Operation: k - (W) → (W) Status Affected: C, DC, Z Status Affected: SLEEP Encoding: Description: TO, PD Encoding: 00 0000 0110 0011 11 Words: 1 Cycles: 1 Words: 1 Example 1: Cycles: 1 Q Cycle Activity: Q Cycle Activity: kkkk kkkk The W register is subtracted (2’s complement method) from
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PIC16C71X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (dest) Operation: (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) Status Affected: None SUBWF f,d Status Affected: C, DC, Z Encoding: Description: 00 1 Cycles: 1 Example 1: dfff ffff Subtract (2’s complement method) W register from register 'f'.
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PIC16C71X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] Syntax: [label] Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .XOR. k → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: Z Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: Description: 11 1 Cycles: 1 Example: 1010 kkkk kkkk The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
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PIC16C71X 10.0 DEVELOPMENT SUPPORT 10.
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PIC16C71X 10.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
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PIC16C71X MPASM has the following features to assist in developing software for specific use applications. • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability. • Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems. • Supports Hex (default), Decimal and Octal source and listing formats.
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Emulator Products Software Tools DS30272A-page 88 Programmers ✔ KEELOQ Evaluation Kit  PICDEM-3 PICDEM-2 PICDEM-1 SEEVAL Designers Kit  KEELOQ Programmer PRO MATE II Universal Programmer  PICSTART Plus Low-Cost Universal Dev. Kit  PICSTART Lite Ultra Low-Cost Dev. Kit Total Endurance Software Model ✔ ✔ ✔ fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev.
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PIC16C71X Applicable Devices 11.0 710 71 711 715 ELECTRICAL CHARACTERISTICS FOR PIC16C710 AND PIC16C711 Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................. -55 to +125˚C Storage temperature ..............................................................................................................................
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PIC16C71X Applicable Devices 11.
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PIC16C71X Applicable Devices 11.2 DC Characteristics: PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) -40˚C ≤ TA ≤ +125˚C (extended) DC CHARACTERISTICS Param No. D001 710 71 711 715 Characteristic Sym Min Typ† Max Units Supply Voltage Commercial/Industrial Extended VDD VDD 2.5 3.0 - 6.0 6.
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PIC16C71X Applicable Devices 11.3 710 71 711 715 DC Characteristics: PIC16C710-04 (Commercial, Industrial, Extended) PIC16C711-04 (Commercial, Industrial, Extended) PIC16C710-10 (Commercial, Industrial, Extended) PIC16C711-10 (Commercial, Industrial, Extended) PIC16C710-20 (Commercial, Industrial, Extended) PIC16C711-20 (Commercial, Industrial, Extended) PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param No.
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PIC16C71X Applicable Devices DC CHARACTERISTICS Param No. Characteristic Output Low Voltage I/O ports D080 Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) -40˚C ≤ TA ≤ +125˚C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Sym Min Typ Max Units Conditions † VOL - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.
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PIC16C71X Applicable Devices 11.4 710 71 711 715 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
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PIC16C71X Applicable Devices 11.5 710 71 711 715 Timing Diagrams and Specifications FIGURE 11-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 11-2: Parameter No.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 11-1 for load conditions. TABLE 11-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 11-1 for load conditions. FIGURE 11-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-6: TIMER0 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 TMR0 Note: Refer to Figure 11-1 for load conditions. TABLE 11-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width Min No Prescaler With Prescaler No Prescaler With Prescaler 42 Tt0P 48 T0CKI Period Tcke2tmrI Delay from external clock edge to timer increment * † 0.
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PIC16C71X Applicable Devices TABLE 11-6: A/D CONVERTER CHARACTERISTICS: PIC16C710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-10 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) Param Sym Characteristic No.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-7: A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 11-7: Param No.
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PIC16C71X Applicable Devices 12.0 710 71 711 715 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C710 AND PIC16C711 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-3: TYPICAL IPD vs. VDD @ 25°C (WDT ENABLED, RC MODE) FIGURE 12-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 22 pF, T = 25°C 6.0 25 5.5 5.0 4.5 Fosc(MHz) IPD(µA) 20 15 10 R = 5k 4.0 3.5 3.0 R = 10k 2.5 2.0 5 1.5 1.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 2.5 VDD(Volts) FIGURE 12-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE) 35 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 6.0 Shaded area is beyond recommended range.
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PIC16C71X Applicable Devices FIGURE 12-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE) 710 71 711 715 FIGURE 12-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) 1400 1200 30 25 Device NOT in Brown-out Reset 800 20 600 400 200 0 2.5 IPD(µA) IPD(µA) 1000 Device in Brown-out Reset 15 10 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 5 6.0 0 2.5 The shaded region represents the built-in hysteresis of the brown-out reset circuitry. FIGURE 12-9: MAXIMUM IPD vs.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V IDD(µA) 1400 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency(MHz) 3.5 4.0 4.5 Shaded area is beyond recommended range FIGURE 12-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V IDD(µA) 1400 4.0V 1200 3.5V 1000 3.0V 800 2.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(µA) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz) FIGURE 12-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(µA) 3.5V 3.0V 800 2.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V IDD(µA) 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 12-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 IDD(µA) 3.5V 3.0V 600 2.
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PIC16C71X Applicable Devices FIGURE 12-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE) FIGURE 12-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD 600 4.0 Max -40°C 5.0V 500 3.5 3.0 gm(mA/V) 4.0V 400 IDD(µA) 710 71 711 715 3.0V 300 200 2.5 Typ 25°C 2.0 Min 85°C 1.5 1.0 100 0.5 0 20 pF 100 pF RC OSCILLATOR FREQUENCIES 100 300 pF 5k 4.12 MHz ± 1.4% 10k 2.35 MHz ± 1.4% 100k 268 kHz ± 1.1% 5.5 6.0 6.5 7.0 70 60 1.80 MHz ± 1.0% 1.27 MHz ± 1.0% 10k 688 kHz ± 1.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25°C) FIGURE 12-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25°C) 3.5 70 3.0 60 50 Startup Time(ms) Startup Time(Seconds) 2.5 2.0 32 kHz, 33 pF/33 pF 1.5 1.0 40 200 kHz, 68 pF/68 pF 30 200 kHz, 47 pF/47 pF 20 1 MHz, 15 pF/15 pF 10 0.5 4 MHz, 15 pF/15 pF 200 kHz, 15 pF/15 pF 0.0 2.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 6.0 4.0 4.5 VDD(Volts) 5.0 5.5 6.
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PIC16C71X Applicable Devices FIGURE 12-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25°C) 710 71 711 715 FIGURE 12-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25°C) 1800 1600 6.0V 1400 5.5V 120 100 5.0V 1200 4.5V 1000 4.0V 60 40 20 0 0 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V IDD(µA) IDD(µA) 80 3.5V 800 3.0V 600 2.5V 400 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 12-26: MAXIMUM IDD vs.
PAGE 110
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25°C) 7.0 FIGURE 12-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40°C TO 85°C) 7.0 6.0 6.0 5.0 IDD(mA) IDD(mA) 5.0 4.0 3.0 2.0 1.0 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4.0 3.0 2.0 1.0 4 6 8 10 12 Frequency(MHz) 14 16 18 20 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4 6 8 10 12 14 16 18 20 Frequency(MHz) DS30272A-page 110  1997 Microchip Technology Inc.
PAGE 111
PIC16C71X Applicable Devices 13.0 710 71 711 715 ELECTRICAL CHARACTERISTICS FOR PIC16C715 Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125˚C Storage temperature .............................................................................................................................. -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD and MCLR)..........
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PIC16C71X 710 71 711 715  1997 Microchip Technology Inc. CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C715-04 PIC16C715-10 PIC16C715-20 PIC16LC715-04 PIC16C715/JW VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 3.0V IDD: 5 mA max. at 5.5V RC IPD: 21 µA max. at 4V IPD: 1.5 µA typ. at 4V IPD: 1.
PAGE 113
PIC16C71X Applicable Devices 13.1 DC Characteristics: PIC16C715-04 (Commercial, Industrial, Extended) PIC16C715-10 (Commercial, Industrial, Extended) PIC16C715-20 (Commercial, Industrial, Extended)) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) -40˚C ≤ TA ≤ +125˚C (extended) DC CHARACTERISTICS Param. No. Characteristic 710 71 711 715 Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.
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PIC16C71X Applicable Devices 13.2 710 71 711 715 DC Characteristics: PIC16LC715-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 2.5 - 5.5 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PAGE 115
PIC16C71X Applicable Devices 13.3 DC Characteristics: PIC16C715-04 (Commercial, Industrial, Extended) PIC16C715-10 (Commercial, Industrial, Extended) PIC16C715-20 (Commercial, Industrial, Extended) PIC16LC715-04 (Commercial, Industrial)) DC CHARACTERISTICS Param No.
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PIC16C71X Applicable Devices 710 71 711 715 DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports (Note 3) D090 Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) -40˚C ≤ TA ≤ +125˚C (extended) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Sym Min Typ Max Units Conditions † VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.
PAGE 117
PIC16C71X Applicable Devices 13.4 710 71 711 715 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PAGE 118
PIC16C71X Applicable Devices 13.5 710 71 711 715 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKOUT TABLE 13-2: Parameter No. CLOCK TIMING REQUIREMENTS Sym Characteristic Min Typ† Max Units Conditions Fos External CLKIN Frequency (Note 1) DC DC DC DC DC 0.
PAGE 119
PIC16C71X Applicable Devices 710 71 711 715 Q2 Q3 FIGURE 13-3: CLKOUT AND I/O TIMING Q1 Q4 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 13-1 for load conditions. TABLE 13-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PAGE 120
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Parity Error Reset 36 Watchdog Timer RESET 34 31 34 I/O Pins FIGURE 13-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PAGE 121
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 13-6: TIMER0 CLOCK TIMINGS RA4/T0CKI 41 40 42 TMR0 Note: Refer to Figure 13-1 for load conditions. TABLE 13-5: TIMER0 CLOCK REQUIREMENTS Param No. Sym Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period Min No Prescaler With Prescaler No Prescaler With Prescaler 48 Tcke2tmrI Delay from external clock edge to timer increment * † 0.
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PIC16C71X Applicable Devices TABLE 13-6: Parameter No.
PAGE 123
PIC16C71X Applicable Devices TABLE 13-7: Parameter No.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 13-7: A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 13-8: A/D CONVERSION REQUIREMENTS Parameter No. Sym Characteristic Min 130 TAD A/D clock period 1.
PAGE 125
PIC16C71X Applicable Devices 14.0 710 71 711 715 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C715 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
PAGE 126
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-3: TYPICAL IPD vs. VDD @ 25°C (WDT ENABLED, RC MODE) FIGURE 14-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 22 pF, T = 25°C 6.0 25 5.5 5.0 20 Fosc(MHz) IPD(µA) 4.5 15 10 R = 5k 4.0 3.5 3.0 R = 10k 2.5 2.0 5 1.5 0 2.5 1.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) 0.0 2.5 Shaded area is beyond recommended range. FIGURE 14-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE) 35 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 6.
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PIC16C71X Applicable Devices FIGURE 14-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE) 710 71 711 715 FIGURE 14-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) 1400 30 1200 25 Device NOT in Brown-out Reset 800 20 600 400 200 0 2.5 IPD(µA) IPD(µA) 1000 Device in Brown-out Reset 15 10 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 5 6.0 0 2.5 This shaded region represents the built-in hysteresis of the brown-out reset circuitry. 3.0 3.5 4.0 4.5 VDD(Volts) 5.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C) 2000 1800 5.5V 5.0V 1600 4.5V IDD(µA) 1400 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency(MHz) 3.5 4.0 4.5 Shaded area is beyond recommended range FIGURE 14-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C) 2000 1800 5.5V 5.0V 1600 4.5V IDD(µA) 1400 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.
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PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C) 1600 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(µA) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz) FIGURE 14-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C) 1600 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(µA) 3.5V 3.0V 800 2.
PAGE 130
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C) 1200 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V IDD(µA) 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 14-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C) 1200 5.5V 1000 5.0V 4.5V 4.0V 800 IDD(µA) 3.5V 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) DS30272A-page 130  1997 Microchip Technology Inc.
PAGE 131
PIC16C71X Applicable Devices FIGURE 14-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE) FIGURE 14-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD 600 4.0 Max -40°C 5.0V 500 3.5 3.0 gm(mA/V) 4.0V 400 IDD(µA) 710 71 711 715 3.0V 300 200 2.5 Typ 25°C 2.0 Min 85°C 1.5 1.0 100 0.5 0 20 pF 100 pF 0.0 3.0 300 pF Capacitance(pF) TABLE 14-1: Rext 300 pF 5.0 5.5 VDD(Volts) 6.0 6.5 7.0 110 100 5k 4.12 MHz ± 1.4% 90 10k 2.35 MHz ± 1.4% 80 100k 268 kHz ± 1.1% 3.3k 1.
PAGE 132
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25°C) FIGURE 14-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25°C) 3.5 70 3.0 60 50 Startup Time(ms) Startup Time(Seconds) 2.5 2.0 32 kHz, 33 pF/33 pF 1.5 1.0 40 200 kHz, 68 pF/68 pF 30 200 kHz, 47 pF/47 pF 20 1 MHz, 15 pF/15 pF 10 0.5 0.0 2.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TABLE 14-2: FIGURE 14-23: TYPICAL XTAL STARTUP TIME vs.
PAGE 133
PIC16C71X Applicable Devices FIGURE 14-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25°C) 710 71 711 715 FIGURE 14-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25°C) 1800 1600 120 5.5V 1400 100 5.0V 1200 4.5V 1000 4.0V 60 40 20 0 0 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V IDD(µA) IDD(µA) 80 3.5V 800 3.0V 600 2.5V 400 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 14-26: MAXIMUM IDD vs.
PAGE 134
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25°C) 7.0 FIGURE 14-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40°C TO 85°C) 7.0 6.0 6.0 5.0 IDD(mA) IDD(mA) 5.0 4.0 3.0 2.0 1.0 0.0 1 2 5.5V 5.0V 4.5V 4.0V 4.0 3.0 2.0 1.0 4 6 8 10 12 Frequency(MHz) 14 16 18 20 0.0 1 2 5.5V 5.0V 4.5V 4.0V 4 6 8 10 12 14 16 18 20 Frequency(MHz) DS30272A-page 134  1997 Microchip Technology Inc.
PAGE 135
PIC16C71X Applicable Devices 15.0 710 71 711 715 ELECTRICAL CHARACTERISTICS FOR PIC16C71 Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125˚C Storage temperature .............................................................................................................................. -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).....
PAGE 136
PIC16C71X Applicable Devices 15.1 710 71 711 715 DC Characteristics: PIC16C71-04 (Commercial, Industrial) PIC16C71-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) DC CHARACTERISTICS Param No. Characteristic Sym Min D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PAGE 137
PIC16C71X Applicable Devices 15.2 DC Characteristics: PIC16LC71-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) OOperating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) DC CHARACTERISTICS Param No. Characteristic 710 71 711 715 Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 3.0 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PAGE 138
PIC16C71X Applicable Devices 15.3 710 71 711 715 DC Characteristics: PIC16C71-04 (Commercial, Industrial) PIC16C71-20 (Commercial, Industrial) PIC16LC71-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
PAGE 139
PIC16C71X Applicable Devices DC CHARACTERISTICS Param No. Characteristic Capacitive Loading Specs on Output Pins OSC2 pin D100 D101 † Note 1: 2: 3: 4: 710 71 711 715 Standard Operating Conditions (unless otherwise stated) OOperating temperature 0˚C ≤ TA ≤ +70˚C (commercial) -40˚C ≤ TA ≤ +85˚C (industrial) Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2.
PAGE 140
PIC16C71X Applicable Devices 15.4 710 71 711 715 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PAGE 141
PIC16C71X Applicable Devices 15.5 710 71 711 715 Timing Diagrams and Specifications FIGURE 15-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 15-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Fosc External CLKIN Frequency (Note 1) Min Typ† Max Units Conditions DC — 4 MHz XT osc mode DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.
PAGE 142
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 15-1 for load conditions. TABLE 15-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PAGE 143
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 15-1 for load conditions. TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PAGE 144
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-5: TIMER0 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 TMR0 Note: Refer to Figure 15-1 for load conditions. TABLE 15-5: Param No. 40* TIMER0 EXTERNAL CLOCK REQUIREMENTS Sym Characteristic Tt0H T0CKI High Pulse Width Min No Prescaler With Prescaler 41* Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* Tt0P T0CKI Period No Prescaler With Prescaler * † Typ† Max Units Conditions 0.5TCY + 20 — — ns 10 — — ns 0.
PAGE 145
PIC16C71X Applicable Devices TABLE 15-6: Param No. A01 A02 A/D CONVERTER CHARACTERISTICS Sym Characteristic NR Resolution EABS Absolute error PIC16C71 PIC16LC71 A03 EIL Integral linearity error A04 EDL Differential linearity error A05 EFS Full scale error A06 EOFF Offset error PIC16C71 PIC16LC71 PIC16C71 PIC16LC71 PIC16C71 PIC16LC71 PIC16C71 PIC16LC71 A10 — 710 71 711 715 Monotonicity Min Typ† Max Units Conditions — — 8 bits bits VREF = VDD = 5.
PAGE 146
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-6: A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-7: A/D CONVERSION REQUIREMENTS Param No.
PAGE 147
PIC16C71X Applicable Devices 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C71 FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD 5.0 R = 4.7k The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
PAGE 148
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD TABLE 16-1: RC OSCILLATOR FREQUENCIES .8 Average R = 3.3k Cext Rext FOSC @ 5V, 25°C .7 20 pF 4.7k 10k 100k 3.3k 4.7k 10k 100k 3.3k 4.7k 10k 100k R = 4.7k .6 Fosc (MHz) 100 pF .5 300 pF .4 R = 10k .3 Cext = 300 pF, T = 25°C R = 100k 0 3.0 3.5 4.0 ±17.35% ±10.10% ±11.90% ±9.43% ±9.83% ±10.92% ±16.03% ±10.97% ±10.14% ±10.43% ±11.
PAGE 149
PIC16C71X Applicable Devices FIGURE 16-7: MAXIMUM IPD VS. VDD WATCHDOG DISABLED 710 71 711 715 FIGURE 16-8: MAXIMUM IPD VS. VDD WATCHDOG ENABLED 45 25 -55°C -40°C 40 125°C 35 20 30 125°C 25 20 0°C 70°C 85°C 15 10 85°C 70°C 10 5 5 0 3.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 0°C -40°C -55°C 6.0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.
PAGE 150
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD 4.50 VIH, Max (-40°C to 85°C) VIH, Typ (25°C) 4.00 VIH, Min (-40°C to 85°C) VIH, VIL (Volts) 3.50 3.00 2.50 2.00 1.50 VIL, Max (-40°C to 85°C) 1.00 VIL, Typ (25°C) VIL, Min (-40°C to 85°C) 0.50 0.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Note: These input pins have a Schmitt Trigger input buffer. FIGURE 16-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) VS.
PAGE 151
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-12: TYPICAL IDD VS. FREQ (EXT CLOCK, 25°C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 100 10 1 10,000 100,000 1,000,000 100,000,000 10,000,000 Frequency (Hz) FIGURE 16-13: MAXIMUM, IDD VS. FREQ (EXT CLOCK, -40° TO +85°C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 IDD (µA) 1,000 100 10 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz)  1997 Microchip Technology Inc. DS30272A-page 151 Data based on matrix samples.
PAGE 152
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-14: MAXIMUM IDD VS. FREQ WITH A/D OFF (EXT CLOCK, -55° TO +125°C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 IDD (µA) 1,000 10 10,000 100,000 1,000,000 100,000,000 10,000,000 Frequency (Hz) FIGURE 16-15: WDT TIMER TIME-OUT PERIOD VS. VDD FIGURE 16-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR VS. VDD 9000 50 8000 45 7000 40 Max, -40°C 35 gm (µA/V) 6000 WDT Period (ms) Data based on matrix samples. See first page of this section for details.
PAGE 153
PIC16C71X Applicable Devices FIGURE 16-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR VS. VDD 710 71 711 715 FIGURE 16-19: IOH VS. VOH, VDD = 3V 0 225 200 -5 Max, -40°C Min, 85°C 175 -10 Typ, 25°C IOH (mA) gm (µA/V) 150 125 100 Min, 85°C Typ, 25°C -15 Max, -40°C 50 -20 25 0 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 FIGURE 16-18: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR VS. VDD -25 0.0 0.5 1.0 1.5 2.0 VOH (Volts) 2.5 3.0 FIGURE 16-20: IOH VS.
PAGE 154
PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-22: IOL VS. VOL, VDD = 5V FIGURE 16-21: IOL VS. VOL, VDD = 3V 35 90 Max @ -40°C 30 80 Max @ -40°C 70 25 60 Typ @ 25°C Typ @ 25°C 15 Min @ +85°C IOL (mA) IOL (mA) 20 50 Min @ +85°C 40 30 10 20 Data based on matrix samples. See first page of this section for details. 5 10 0 0.0 0.5 1.0 1.5 VOL (Volts) 2.0 2.5 3.0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOL (Volts) DS30272A-page 154  1997 Microchip Technology Inc.
PAGE 155
PIC16C71X 17.0 PACKAGING INFORMATION 17.1 18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW) N α C E1 E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A3 A e1 B A2 D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol Min Max Inches Notes Min Max α 0° 10° 0° 10° A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 — 0.381 3.810 3.810 0.355 1.270 0.203 22.352 20.320 7.620 5.588 2.540 7.366 7.620 3.175 18 0.508 0.381 5.080 1.7780 4.
PAGE 156
PIC16C71X 17.2 18-Lead Plastic Dual In-line (300 mil) (P) N α C E1 E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max α 0° A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 7.874 3.048 18 0.889 0.127 DS30272A-page 156 Inches Notes Min Max 10° 0° 10° 4.064 – 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.591 7.
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PIC16C71X 17.3 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)(SO) e B h x 45° N Index Area E H α C Chamfer h x 45° L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max α 0° 8° 0° 8° A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 – 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.
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PIC16C71X 17.4 20-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) N Index area E H α C L 1 2 3 B e A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Symbol Min Max α 0° A A1 B C D E e H L N CP 1.730 0.050 0.250 0.130 7.070 5.200 0.650 7.650 0.550 20 - Inches Notes Min Max 8° 0° 8° 1.990 0.210 0.380 0.220 7.330 5.380 0.650 7.900 0.950 20 0.102 0.068 0.002 0.010 0.005 0.278 0.205 0.026 0.301 0.022 20 - 0.078 0.008 0.015 0.009 0.289 0.212 0.
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PIC16C71X 17.5 Package Marking Information 18-Lead PDIP Example MMMMMMMMMMMMM XXXXXXXXXXXXXXXX AABBCDE 18-Lead SOIC PIC16C711-04/P 9452CBA Example MMMMMMMMMM XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE PIC16C715 -20/50 9447CBA 18-Lead CERDIP Windowed Example MMMMMM XXXXXXXX AABBCDE 20-Lead SSOP Example XXXXXXXX XXXXXXXX PIC16C710 20I/SS025 AABBCAE Legend: 9517SBP MM...M XX...
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PIC16C71X NOTES: DS30272A-page 160  1997 Microchip Technology Inc.
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PIC16C71X APPENDIX A: APPENDIX B: COMPATIBILITY The following are the list of modifications over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (1K now as opposed to 512 before) and register file (68 bytes now versus 32 bytes before).
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PIC16C71X APPENDIX C: WHAT’S NEW APPENDIX D: WHAT’S CHANGED 1. 1. Consolidated all pin compatible 18-pin A/D based devices into one data sheet. 2. 3. DS30272A-page 162 Minor changes, spelling and grammatical changes. Low voltage operation on the PIC16LC710/711/ 715 has been reduced from 3.0V to 2.5V. Part numbers of the PIC16C70 and PIC16C71A have changed to PIC16C710 and PIC16C711, respectively.  1997 Microchip Technology Inc.
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PIC16C71X INDEX A A/D Accuracy/Error ........................................................... 44 ADIF bit ...................................................................... 39 Analog Input Model Block Diagram ............................ 40 Analog-to-Digital Converter ........................................ 37 Configuring Analog Port Pins ..................................... 41 Configuring the Interrupt ............................................ 39 Configuring the Module .........................
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PIC16C71X I I/O Ports PORTA ....................................................................... 25 PORTB ....................................................................... 27 Section ....................................................................... 25 I/O Programming Considerations ....................................... 30 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 85 In-Circuit Serial Programming ...................................... 47, 67 INDF Register ....................
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PIC16C71X RA2/AN2 ...................................................................... 9 RA3/AN3/VREF ............................................................. 9 RA4/T0CKI ................................................................... 9 RB0/INT ....................................................................... 9 RB1 .............................................................................. 9 RB2 .............................................................................. 9 RB3 ........
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PIC16C71X TO bit ................................................................................. 17 TOSE bit ............................................................................. 18 TRISA Register ...................................................... 14, 16, 25 TRISB Register ...................................................... 14, 16, 27 Two’s Complement ..............................................................
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PIC16C71X Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 8-1: Figure 8-2: Figure 8-3: Figure 8-4: Figure 8-5: Figure 8-6: Figure 8-7: Figure 8-8: Figure 8-9: Figure 8-10: Figure 8-11: Figure 8-12: Figure 8-13: Figure 8-14: Figure 8-15: Figure 8-16: Figure 8-17: Figure 8-18: Figure 8-19: Figure 8-20: Figure 8-21: Figure 8-22: Figure 8-23: Figure 9-1: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 12-1: Figure 12-2: Figure 12-3: Figure 1
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PIC16C71X Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 14-11: Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 14-20: Figure 14-21: Figure 14-22: Figure 14-23: Figure 14-24: Figure 14-25: Figure 14-26: Figure 14-27: Figure 14-28: Figure 14-29: Figure 14-30: Figure 15-1: Figure 15-2: Figure 15-3: Figure 15-4: Figure 15-5: Figure 15-6: Figure 16-1: Figure 16-2: Figure 16-3: Typical RC Oscillator Frequency vs.
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PIC16C71X LIST OF TABLES Table 1-1: Table 3-1: Table 4-1: Table 4-2: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 6-1: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 8-1: Table 8-2: Table 8-3: Table 8-4: Table 8-5: Table 8-6: Table 8-7: Table 8-8: Table 8-9: Table 8-10: Table 8-11: Table 8-12: Table 8-13: Table 9-1: Table 9-2: Table 10-1: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 11-5: PIC16C71X Family of Devices.................... 4 PIC16C710/71/711/715 Pinout Description ..........
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PIC16C71X NOTES: DS30390D-page 170  1997 Microchip Technology Inc.
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PIC16C71X ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts.
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PIC16C71X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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PIC16C71X PIC16C71X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. Examples PART NO.
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PIC16C71X NOTES: DS30272A-page 174  1997 Microchip Technology Inc.
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PIC16C71X NOTES:  1997 Microchip Technology Inc.
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Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
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M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K.