Datasheet

 1997-2013 Microchip Technology Inc. DS30234E-page 133
PIC16C6X
TRISD 61 62 62A R62 63 R636464AR646565AR6566 67 1111 1111 1111 1111 uuuu uuuu
TRISE
61 62 62A R62 63 R636464AR646565AR6566 67 0000 -111 0000 -111 uuuu -uuu
PIE1
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 00-- 0000 00-- 0000 uu-- uuuu
61 62 62A R62 63 R63 64 64A R646565AR656667 0000 0000 0000 0000 uuuu uuuu
PIE2
61 62 62A R62 63 R63 64 64A R646565AR656667 ---- ---0 ---- ---0 ---- ---u
PCON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---- --0u ---- --uu ---- --uu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---- --0- ---- --u- ---- --u-
PR2
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 1111 1111 1111 1111 1111 1111
SSPADD
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu
SSPSTAT
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 --00 0000 --00 0000 --uu uuuu
TXSTA
61 62 62A R62 63 R63 64 64A R646565AR656667 0000 -010 0000 -010 uuuu -uuu
SPBRG
61 62 62A R62 63 R63 64 64A R646565AR656667 0000 0000 0000 0000 uuuu uuuu
TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register Applicable Devices Power-on Reset
Brown-out
Reset
M
CLR Reset during:
– normal operation
– SLEEP
WDT Reset
Wake-up via
interrupt or
WDT Wake-up
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h)
after execution of PC + 1.
3: See Table 13-10 and Table 13-11 for reset value for specific conditions.