Datasheet

 1997-2013 Microchip Technology Inc. DS30234E-page 97
PIC16C6X
Figure 11-19 and Figure 11-20 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.
FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-20: MASTER-RECEIVER SEQUENCE
FIGURE 11-21: COMBINED FORMAT
For 7-bit address:
S
Slave Address
First 7 bits
SR/W
A1 Slave Address
Second byte
A2
Data A Data P
A master transmitter addresses a slave receiver
with a 10-bit address.
A/A
Slave Address R/W ADataADataA/AP
'0' (write) data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
From master to slave
From slave to master
A = acknowledge (SDA low)
A
= not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
For 7-bit address:
S
Slave Address
First 7 bits
SR/W
A1 Slave Address
Second byte
A2
A master transmitter addresses a slave receiver
with a 10-bit address.
Slave Address R/W
ADataAData A P
'1' (read) data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
From master to slave
From slave to master
A = acknowledge (SDA low)
A
= not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
Slave Address
First 7 bits
Sr R/W A3 AData A PData
(read)
Combined format:
S
Combined format - A master addresses a slave with a 10-bit address, then transmits
Slave Address R/W ADataA/ASr P
(read) Sr = repeated
Transfer direction of data and acknowledgment bits depends on R/W
bits.
From master to slave
From slave to master
A = acknowledge (SDA low)
A
= not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Slave Address
First 7 bits
Sr R/W A
(write)
data to this slave and reads data from this slave.
Slave Address
Second byte
Data Sr Slave Address
First 7 bits
R/W
ADataA APA ADataA/A Data
(read)
Slave Address R/W
ADataA/A
Start Condition
(write) Direction of transfer
may change at this point
(read or write)
(n bytes + acknowledge)
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67