Datasheet

1997-2013 Microchip Technology Inc. DS30234E-page 47
PIC16C6X
4.2.2.8 PCON REGISTER
The Power Control register (PCON) contains a flag bit
to allow differentiation between a Power-on Reset to an
external MCLR
reset or WDT reset. Those devices with
brown-out detection circuitry contain an additional bit to
differentiate a Brown-out Reset condition from a Power-
on Reset condition.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR
is
clear, indicating a brown-out has occurred.
The BOR
status bit is a “don't care” and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
FIGURE 4-22: PCON REGISTER FOR PIC16C62/64/65 (ADDRESS 8Eh)
FIGURE 4-23: PCON REGISTER FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67
(ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
—POR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
q = value depends on conditions
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: Reserved
This bit should be set upon a Power-on Reset by user software and maintained as set. Use of this bit as a general
purpose read/write bit is not recommended, since this may affect upward compatibility with future products.
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
—PORBOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
q = value depends on conditions
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)