Datasheet
1997-2013 Microchip Technology Inc. DS30234E-page 33
PIC16C6X
Bank 1
80h
(1)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
(1)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h
(1)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h
(1)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA
— — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h
(5)
TRISD
PORTD Data Direction Register 1111 1111 1111 1111
89h
(5)
TRISE
IBF OBF IBOV PSPMODE
— PORTE Data Direction Bits 0000 -111 0000 -111
8Ah
(1,2)
PCLATH — — —
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
8Bh
(1)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1
PSPIE
(6)
(4) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh
PIE2
— — — — — — —CCP2IE---- ---0 ---- ---0
8Eh PCON
— — — — — —POR
BOR
---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD
Synchronous Serial Port (I
2
C mode) Address Register
0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h
TXSTA
CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 0000 -010
99h
SPBRG
Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh — Unimplemented — —
TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR
and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.