Datasheet

PIC16C6X
DS30234E-page 276  1997-2013 Microchip Technology Inc.
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 22-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 22-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 22-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
120* TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
PIC16C66/67 — — 80 ns
PIC16LC66/67 — — 100 ns
121* Tckrf Clock out rise time and fall time
(Master Mode)
PIC16C66/67 — — 45 ns
PIC16LC66/67 — — 50 ns
122* Tdtrf Data out rise time and fall time PIC16C66/67 — — 45 ns
PIC16LC66/67 — — 50 ns
* These parameters are characterized but not tested.
†: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
125* TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK  (DT setup time) 15 — — ns
126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns
* These parameters are characterized but not tested.
†: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 22-1 for load conditions
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 22-1 for load conditions
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin