Datasheet

 1997-2013 Microchip Technology Inc. DS30234E-page 141
PIC16C6X
13.8 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, status bit P
D (STATUS<3>) is cleared,
status bit T
O (STATUS<4>) is set, and the oscillator
driver is turned off. The I/O ports maintain the status
they had before the SLEEP instruction was executed
(driving high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
DD, or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, and disable
external clocks. Pull all I/O pins, that are hi-impedance
inputs, high or low externally to avoid switching currents
caused by floating inputs. The T0CKI input should also
be at V
DD or VSS for lowest current consumption. The
contribution from on-chip pull-ups on PORTB should be
considered.
The MCLR
/VPP pin must be at a logic high level
(V
IHMC).
13.8.1 WAKE-UP FROM SLEEP
The device can wake from SLEEP through one of the
following events:
1. External reset input on MCLR
/VPP pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from RB0/INT pin, RB port change, or
some peripheral interrupts.
External MCLR
Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO
and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD
bit, which is set on
power-up is cleared when SLEEP is invoked. The TO
bit
is cleared if WDT time-out occurred (and caused wake-
up).
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2. SSP (Start/Stop) bit detect interrupt.
3. SSP transmit or receive in slave mode (SPI/I
2
C).
4. CCP capture mode interrupt.
5. Parallel Slave Port read or write.
6. USART TX or RX (synchronous slave mode).
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
13.8.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO
bit will not
be set and PD
bits will not be cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme-
diately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO
bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD
bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.