Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 8-Bit 4 MHz I/O number 22

 1997-2013 Microchip Technology Inc. DS30234E-page 1

PIC16C6X

8-Bit CMOS Microcontrollers

Devices included in this data sheet:

PIC16C6X Microcontroller Core Features:

• High performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• PIC16C61 • PIC16C64A

• PIC16C62 • PIC16CR64

• PIC16C62A • PIC16C65

• PIC16CR62 • PIC16C65A

• PIC16C63 • PIC16CR65

• PIC16CR63 • PIC16C66

• PIC16C64 • PIC16C67

• Low-power, high-speed CMOS EPROM/ROM

technology

• Fully static design

• Wide operating voltage range: 2.5V to 6.0V

• Commercial, Industrial, and Extended

temperature ranges

• Low-power consumption:

 < 2 mA @ 5V, 4 MHz

 15 A typical @ 3V, 32 kHz

 < 1 A typical standby current

PIC16C6X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler,

can be incremented during sleep via

external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period

• Capture/Compare/PWM (CCP) module(s)

• Capture is 16-bit, max resolution is 12.5 ns,

Compare is 16-bit, max resolution is 200 ns,

PWM max resolution is 10-bit.

• Synchronous Serial Port (SSP) with SPI and I



• Universal Synchronous Asynchronous Receiver

Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with

external RD

, WR and CS controls

• Brown-out detection circuitry for

Brown-out Reset (BOR)

PIC16C6X Features 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Program Memory

(EPROM) x 14

1K 2K 2K — 4K — 2K 2K — 4K 4K — 8K 8K

(ROM) x 14 — — — 2K — 4K — — 2K — — 4K — —

Data Memory (Bytes) x 8 36 128 128 128 192 192 128 128 128 192 192 192 368 368

I/O Pins 13 22 22 22 22 22 33 33 33 33 33 33 22 33

Parallel Slave Port — — — — — — Yes Yes Yes Yes Yes Yes — Yes

Capture/Compare/PWM

Module(s)

—1112211122222

Timer Modules 13333333333333

Serial Communication

—SPI/

SPI/

SPI/I

USART

SPI/I

USART

SPI/

SPI/I

USART

SPI/I

USART

SPI/I

USART

SPI/I

USART

SPI/I

USART

In-Circuit Serial

Programming

Ye s Ye s Ye s Ye s Yes Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s

B r o w n -o u t R e s et — — Ye s Yes Ye s Ye s — Ye s Ye s — Yes Ye s Ye s Ye s

Interrupt Sources 3 7 7 7 10 10 8 8 8 11 11 11 10 11

Sink/Source Current (mA) 25/20 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25

Summary of content (334 pages)

PAGE 1
PIC16C6X 8-Bit CMOS Microcontrollers Devices included in this data sheet: • PIC16C61 • PIC16C64A • PIC16C62 • PIC16CR64 • PIC16C62A • PIC16C65 • PIC16CR62 • PIC16C65A • PIC16C63 • PIC16CR65 • PIC16CR63 • PIC16C66 • PIC16C64 • PIC16C67 • Low-power, high-speed CMOS EPROM/ROM technology • Fully static design • Wide operating voltage range: 2.5V to 6.
PAGE 2
PIC16C6X Pin Diagrams PDIP, SOIC, Windowed CERDIP SDIP, SOIC, SSOP, Windowed CERDIP (300 mil) RA2 1 18 RA1 RA3 2 17 RA0 RA4/T0CKI 3 16 OSC1/CLKIN MCLR/VPP 4 15 OSC2/CLKOUT VSS 5 14 VDD RB0/INT 6 13 RB7 RB1 7 12 RB6 RB2 8 11 RB5 RB3 9 10 RB4 MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS PIC16C61 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 OSC1/CLKIN OSC2/CLKOUT 9 10 20 19 RC0/T1OSI/T1CKI RC1/T1OSO RC2/CCP1 RC3/SCK/SCL 11 12 13 14 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB
PAGE 3
PIC16C6X PLCC RC7 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 6 5 4 3 2 1 44 43 42 41 40 MQFP RA3 RA2 RA1 RA0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC RC6 RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSO NC Pin Diagrams (Cont.
PAGE 4
PIC16C6X Table Of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 General Description ....................................................................................................................................................................... 5 PIC16C6X Device Varieties ...........................................................................................................................................................
PAGE 5
PIC16C6X 1.0 GENERAL DESCRIPTION The PIC16CXX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with separate 8-bit wide data.
PAGE 6
PIC16C6X TABLE 1-1: PIC16C6X FAMILY OF DEVICES PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63 Maximum Frequency of Operation (MHz) 20 20 20 20 20 EPROM Program Memory (x14 words) 1K 2K — 4K — ROM Program Memory (x14 words) — — 2K — 4K Data Memory (bytes) 36 128 128 192 192 Timer Module(s) TMR0 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/ Peripherals PWM Module(s) — 1 1 2 2 Serial Port(s) (SPI/I2C, USART) — SPI/I2C SPI/I2C
PAGE 7
PIC16C6X 2.0 PIC16C6X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C6X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C6X family of devices, there are four device “types” as indicated in the device number: 1.
PAGE 8
PIC16C6X NOTES: DS30234E-page 8  1997-2013 Microchip Technology Inc.
PAGE 9
PIC16C6X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data may be fetched from the same memory using the same bus.
PAGE 10
PIC16C6X FIGURE 3-1: PIC16C61 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RAM File Registers 36 x 8 8 Level Stack (13-bit) 1K x 14 8 Data Bus Program Counter EPROM RAM Addr (1) RA4/T0CKI PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg RB0/INT RB7:RB1 STATUS reg 8 Power-up Timer Instruction Decode & Control Timing Generation 3 Oscillator Start-up Timer Power-on Reset Watchdog Timer MUX ALU 8 W reg OSC1/CLKIN OSC2/CLKOUT Timer0 MCL
PAGE 11
PIC16C6X FIGURE 3-2: PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM 13 Program Bus 14 PORTA RA0 RA1 RA2 RA3 RAM File Registers 128 x 8 8 Level Stack (13-bit) 2K x 14 8 Data Bus Program Counter EPROM/ ROM Program Memory RAM Addr(1) RA4/T0CKI RA5/SS PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 PORTC Power-up Timer 3 Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation Watchdog Timer Brown-out Res
PAGE 12
PIC16C6X FIGURE 3-3: PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RAM File Registers 192 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr(1) RA5/SS PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 PORTC Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT 3 Oscillator Start-up Timer Power-on Reset Watchdog Timer
PAGE 13
PIC16C6X FIGURE 3-4: PIC16C66/67 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RAM File Registers 368 x 8 8 Level Stack (13-bit) 8K x 14 8 Data Bus Program Counter EPROM RAM Addr(1) RA5/SS PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 PORTC Power-up Timer 3 Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation Watchdog Timer OSC1/CLKIN OSC2/CLKOUT ALU 8 W
PAGE 14
PIC16C6X TABLE 3-1: PIC16C61 PINOUT DESCRIPTION Pin Name DIP Pin# SOIC Pin# Pin Type Buffer Type Description ST/CMOS(1) Oscillator crystal input/external clock source input. OSC1/CLKIN 16 16 I OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PAGE 15
PIC16C6X TABLE 3-2: PIC16C62/62A/R62/63/R63/66 PINOUT DESCRIPTION Pin Name Pin# Pin Type Buffer Type Description OSC1/CLKIN 9 I ST/CMOS(3) OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 I/P ST Master clear reset input or programming voltage input. This pin is an active low reset to the device.
PAGE 16
PIC16C6X TABLE 3-3: PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION Pin Name DIP Pin# PLCC Pin# TQFP MQFP Pin# Pin Type Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PAGE 17
PIC16C6X TABLE 3-3: Pin Name PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION (Cont.’d) DIP Pin# PLCC Pin# TQFP MQFP Pin# Pin Type Buffer Type Description PORTD can be a bi-directional I/O port or parallel slave port for interfacing to a microprocessor bus.
PAGE 18
PIC16C6X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clock and instruction execution flow is shown in Figure 3-5.
PAGE 19
PIC16C6X 4.0 MEMORY ORGANIZATION FIGURE 4-2: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Program Memory Organization The PIC16C6X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space.
PAGE 20
PIC16C6X FIGURE 4-4: PIC16C66/67 PROGRAM MEMORY MAP AND STACK User Memory Space PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1    Stack Level 8 For the PIC16C61, general purpose register locations 8Ch-AFh of Bank 1 are not physically implemented. These locations are mapped into 0Ch-2Fh of Bank 0.
PAGE 21
PIC16C6X FIGURE 4-6: PIC16C62/62A/R62/64/64A/ R64 REGISTER FILE MAP File Address File Address FIGURE 4-7: PIC16C63/R63/65/65A/R65 REGISTER FILE MAP File Address File Address 00h INDF(1) INDF(1) 80h 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h
PAGE 22
PIC16C6X FIGURE 4-8: PIC16C66/67 DATA MEMORY MAP File Address Indirect addr.
PAGE 23
PIC16C6X 4.2.2 SPECIAL FUNCTION REGISTERS: The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. TABLE 4-1: Address Name The special function registers can be classified into two sets (core and peripheral).
PAGE 24
PIC16C6X TABLE 4-2: SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA
PAGE 25
PIC16C6X TABLE 4-2: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 (Cont.
PAGE 26
PIC16C6X TABLE 4-3: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA 06h
PAGE 27
PIC16C6X TABLE 4-3: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 (Cont.
PAGE 28
PIC16C6X TABLE 4-4: SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA
PAGE 29
PIC16C6X TABLE 4-4: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 (Cont.
PAGE 30
PIC16C6X TABLE 4-5: SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB PORTB Dat
PAGE 31
PIC16C6X TABLE 4-5: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 (Cont.
PAGE 32
PIC16C6X TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA 06h
PAGE 33
PIC16C6X TABLE 4-6: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.
PAGE 34
PIC16C6X TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.
PAGE 35
PIC16C6X 4.2.2.1 STATUS REGISTER Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The STATUS register, shown in Figure 4-9, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register.
PAGE 36
PIC16C6X 4.2.2.2 OPTION REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for TMR0 register, assign the prescaler to the Watchdog Timer.
PAGE 37
PIC16C6X 4.2.2.3 INTCON REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The INTCON Register is a readable and writable register which contains the various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PAGE 38
PIC16C6X 4.2.2.4 PIE1 REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch) RW-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear.
PAGE 39
PIC16C6X FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear.
PAGE 40
PIC16C6X FIGURE 4-15: PIE1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: Reserved: Always maintain this bit clear.
PAGE 41
PIC16C6X 4.2.2.5 PIR1 REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PAGE 42
PIC16C6X FIGURE 4-17: PIR1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear.
PAGE 43
PIC16C6X FIGURE 4-18: PIR1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF — — — SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place bit 6: Reserved: Always maintain this bit clear.
PAGE 44
PIC16C6X FIGURE 4-19: PIR1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place bit 6: Reserved: Always maintain this bit clear.
PAGE 45
PIC16C6X 4.2.2.6 PIE2 REGISTER Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 This register contains the CCP2 interrupt enable bit. FIGURE 4-20: PIE2 REGISTER (ADDRESS 8Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE bit7 bit0 bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt  1997-2013 Microchip Technology Inc.
PAGE 46
PIC16C6X 4.2.2.7 PIR2 REGISTER . Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 This register contains the CCP2 interrupt flag bit. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PAGE 47
PIC16C6X 4.2.2.8 PCON REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The Power Control register (PCON) contains a flag bit to allow differentiation between a Power-on Reset to an external MCLR reset or WDT reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Poweron Reset condition. FIGURE 4-22: BOR is unknown on Power-on Reset.
PAGE 48
PIC16C6X 4.3 PCL and PCLATH Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-24 shows the two situations for the loading of the PC.
PAGE 49
PIC16C6X Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that the PCLATH is saved and restored by the interrupt service routine (if interrupts are used). 4.5 EXAMPLE 4-1: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.
PAGE 50
PIC16C6X NOTES: DS30234E-page 50  1997-2013 Microchip Technology Inc.
PAGE 51
PIC16C6X 5.0 I/O PORTS FIGURE 5-1: BLOCK DIAGRAM OF THE RA3:RA0 PINS AND THE RA5 PIN Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Some pins for these I/O ports are multiplexed with an alternate function(s) for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 PORTA and TRISA Register Data bus D VDD WR Port Pin RA4/T0CKI is a Schmitt Trigger input and an open drain output.
PAGE 52
PIC16C6X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Type RA0 RA1 RA2 RA3 RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST RA5/SS (1) bit5 TTL Function Input/output Input/output Input/output Input/output Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: The PIC16C61 does not have PORTA<5> or TRISA<5>, read as ‘0’.
PAGE 53
PIC16C6X 5.2 PORTB and TRISB Register Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).
PAGE 54
PIC16C6X FIGURE 5-4: BLOCK DIAGRAM OF THE RB7:RB4 PINS FOR PIC16C62A/63/R63/64A/65A/ R65/66/67 FIGURE 5-5: VDD RBPU(2) weak P pull-up VDD RBPU(2) Data Latch D WR Port D WR Port WR TRIS TRIS Latch D Q TTL Input Buffer I/O pin(1) TRIS Latch D Q I/O pin(1) CK Q CK Q CK WR TRIS Data Latch Data bus weak P pull-up Data bus BLOCK DIAGRAM OF THE RB3:RB0 PINS TTL Input Buffer CK ST Buffer RD TRIS Q RD TRIS Latch Q D EN RD Port EN RD Port Q1 D RB0/INT Set RBIF Schmitt Trigger Buf
PAGE 55
PIC16C6X 5.3 PORTC and TRISC Register FIGURE 5-6: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PORTC is an 8-bit wide bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin.
PAGE 56
PIC16C6X TABLE 5-6: PORTC FUNCTIONS FOR PIC16C62A/R62/64A/R64 Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture input/Compare output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I2C modes.
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PIC16C6X 5.4 PORTD and TRISD Register FIGURE 5-7: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Data bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as input or output. D WR PORT PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
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PIC16C6X 5.5 PORTE and TRISE Register FIGURE 5-8: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Data bus PORTE has three pins, RE2/CS, RE1/WR, and RE0/RD which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. PORTE BLOCK DIAGRAM (IN I/O PORT MODE) D WR PORT Q I/O pin(1) CK Data Latch I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set.
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PIC16C6X TABLE 5-11: PORTE FUNCTIONS Name Bit# Buffer Type RE0/RD bit0 ST/TTL(1) Function Input/output port pin or Read control input in parallel slave port mode. RD 1 = Not a read operation 0 = Read operation. The system reads the PORTD register (if chip selected) RE1/WR bit1 ST/TTL(1) Input/output port pin or Write control input in parallel slave port mode. WR 1 = Not a write operation 0 = Write operation.
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PIC16C6X 5.6 I/O Programming Considerations EXAMPLE 5-4: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 5.6.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
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PIC16C6X 5.7 Parallel Slave Port Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PORTD operates as an 8-bit wide parallel slave port (microprocessor port) when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input (RE0/RD) and WR control input pin (RE1/WR). It can directly interface to an 8-bit microprocessor data bus.
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PIC16C6X FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on: POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 xxx
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PIC16C6X 6.0 OVERVIEW OF TIMER MODULES Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 All PIC16C6X devices have three timer modules except for the PIC16C61, which has one timer module. Each module can generate an interrupt to indicate that an event has occurred (i.e., timer overflow). Each of these modules are detailed in the following sections. The timer modules are: 6.
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PIC16C6X NOTES: DS30234E-page 64  1997-2013 Microchip Technology Inc.
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PIC16C6X 7.0 TIMER0 MODULE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module.
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PIC16C6X FIGURE 7-3: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0,W T0 TMR0 PC+2 T0+1 Instruction Execute PC+4 PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W NT0+1 NT0 Read TMR0 reads NT0 Write TMR0 executed FIGURE 7-4: PC+3 MOVF TMR0,W MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 T0 Read TMR0 reads N
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PIC16C6X 7.2 Using Timer0 with External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value.
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PIC16C6X 7.3 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF TMR0, MOVWF TMR0, BSF TMR0,bitx) will clear the prescaler count. When assigned to the Watchdog Timer, a CLRWDT instruction will clear the Watchdog Timer and the prescaler count. The prescaler is not readable or writable.
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PIC16C6X 7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This precaution must be followed even if the WDT is disabled.
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PIC16C6X NOTES: DS30234E-page 70  1997-2013 Microchip Technology Inc.
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PIC16C6X 8.0 TIMER1 MODULE Timer1 also has an internal “reset input”. This reset can be generated by CCP1 or CCP2 (Capture/Compare/ PWM) module. See Section 10.0 for details. Figure 8-1 shows the Timer1 control register. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Timer1 is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. Register TMR1 (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h.
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PIC16C6X 8.1 Timer1 Operation in Timer Mode 8.2.1 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TMR1 after synchronization. Timer mode is selected by clearing bit TMR1CS (T1CON<1>).
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PIC16C6X 8.3 Timer1 Operation in Asynchronous Counter Mode Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and generate an interrupt on overflow which will wake the processor.
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PIC16C6X 8.5 Resetting Timer1 using a CCP Trigger Output 8.6 Resetting of TMR1 Register Pair (TMR1H:TMR1L) Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP2 is implemented on the PIC16C63/R63/65/65A/ R65/66/67 only. The TMR1H and TMR1L registers are not reset to 00h on a POR or any other reset except by the CCP1 or CCP2 special event trigger.
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PIC16C6X 9.0 TIMER2 MODULE 9.1 Timer2 Prescaler and Postscaler Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Timer2 is an 8-bit timer with a prescaler and a postscaler. It is especially suitable as PWM time-base for PWM mode of CCP module(s). TMR2 is a readable and writable register, and is cleared on any device reset.
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PIC16C6X TABLE 9-1: Address REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Name 0Bh,8Bh INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF Value on: POR, BOR Value on all other resets 0000 000x 0000 000u 0Ch PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 module’s register
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PIC16C6X 10.0 CAPTURE/COMPARE/PWM (CCP) MODULE(s) Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP1 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP2 Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM master/slave duty cycle register. Both the CCP1 and CCP2 modules are identical in operation, with the exception of the operation of the special event trigger.
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PIC16C6X FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh) U-0 — bit7 U-0 — R/W-0 CCPxX R/W-0 R/W-0 CCPxY CCPxM3 R/W-0 CCPxM2 R/W-0 R/W-0 CCPxM1 CCPxM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode Unused Compare Mode Unused PWM Mode These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
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PIC16C6X 10.1.4 CCP PRESCALER 10.2.1 There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler.
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PIC16C6X 10.3 PWM Mode 10.3.1 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.
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PIC16C6X EXAMPLE 10-2: PWM PERIOD AND DUTY CYCLE CALCULATION In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. Desired PWM frequency is 78.125 kHz, Fosc = 20 MHz TMR2 prescale = 1 Table 10-3 lists example PWM frequencies and resolutions for Fosc = 20 MHz. The TMR2 prescaler and PR2 values are also shown. 1/78.125 kHz = [(PR2) + 1] • 4 • 1/20 MHz • 1 12.8 s = [(PR2) + 1] • 4 • 50 ns • 1 10.3.
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PIC16C6X TABLE 10-5: Addr REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name 0Bh,8Bh INTCON 10Bh,18Bh Value on: POR, BOR Value on all other Resets RBIF 0000 000x 0000 000u 0000 0000 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF 0Ch PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0Dh(4) PIR2 — — — — — — — CCP2IF 8Ch PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 8Dh(4) PIE2 — — — —
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 11.1 SSP Module Overview PIC16C6X The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
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PIC16C6X 11.2 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 SPI Mode for PIC16C62/62A/R62/63/ R63/64/64A/R64/65/65A/R65 This section contains register definitions and operational characteristics of the SPI module for the PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16CR63, PIC16C64, PIC16C64A, PIC16CR64, PIC16C65, PIC16C65A, PIC16CR65.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 WCOL bit7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 =
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PIC16C6X 11.2.1 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 OPERATION OF SSP MODULE IN SPI MODE Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear enable bit SSPEN, re-initialize SSPCON register, and then set enable bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X point at which it was taken high. External pull-up/ pull-down resistors may be desirable, depending on the application. The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set the for synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 11.3 PIC16C6X SPI Mode for PIC16C66/67 This section contains register definitions and operational characterisitics of the SPI module on the PIC16C66 and PIC16C67 only.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C66/67) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be c
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 11.3.1 SSP MODULE IN SPI MODE FOR PIC16C66/67 The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X FIGURE 11-13: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C66/67) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit3 bit4 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 11-2: Address REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C66/67) Name 0Bh,8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets GIE PEIE T
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 I2C™ Overview 11.4 This section provides an overview of the Inter-Integrated Circuit (I 2C) bus, with Section 11.5 discussing the operation of the SSP module in I 2C mode. The I 2C bus is a two-wire serial interface developed by the Philips® Corporation. The original specification, or standard mode, was for data transfers of up to 100 Kbps. The enhanced specification (fast mode) is also supported.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X ADDRESSING I 2C DEVICES 11.4.2 FIGURE 11-17: SLAVE-RECEIVER ACKNOWLEDGE There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure 11-15). The more complex is the 10-bit address with a R/W bit (Figure 11-16). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this to be a 10-bit address.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X SCL is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 11-21. Figure 11-19 and Figure 11-20 show Master-transmitter and Master-receiver data transfer sequences.
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PIC16C6X 11.4.4 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 MULTI-MASTER 11.2.4.2 Clock Synchronization 2 The I C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur. 11.4.4.1 ARBITRATION Arbitration takes place on the SDA line, while the SCL line is high.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 11.5 SSP I2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer.
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PIC16C6X 11.5.1 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter).
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 11.5.1.2 RECEPTION PIC16C6X An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X 11.5.1.3 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 11.5.2 11.5.3 MASTER MODE In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit.
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Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X FIGURE 11-27: OPERATION OF THE I 2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR  SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Ho
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PIC16C6X 12.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) MODULE minals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.
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PIC16C6X FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 SPEN bit7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN U-0 — R-0 FERR R-0 OERR R-x RX9D bit0 R W U = Readable bit = Writable bit = Unimplemented bit, read as ‘0’ - n = Value at POR reset x = unknown bit 7: SPEN: Serial Port Enable bit (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins when bits TRISC<7:6> are set) 1 = Serial port enabled 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-b
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PIC16C6X 12.1 USART Baud Rate Generator (BRG) EXAMPLE 12-1: CALCULATING BAUD RATE ERROR Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Desired Baud rate = Fosc / (64 (X + 1)) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored.
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PIC16C6X TABLE 12-3: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz KBAUD % ERROR NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53 +1.73 +0.16 +0.16 -1.96 0 - 16 MHz SPBRG value KBAUD (decimal) 255 64 51 16 9 0 255 FOSC = 5.0688 MHz BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW +0.16 +0.16 -0.79 +2.56 0 - 207 51 41 12 7 0 255 NA NA NA 9.766 19.23 75.76 96.15 312.5 500 2500 9.
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PIC16C6X TABLE 12-5: BAUD RATE (K) 9.6 19.2 38.4 57.6 115.2 250 625 1250 BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz KBAUD % ERROR 9.615 19.230 37.878 56.818 113.636 250 625 1250 +0.16 +0.16 -1.36 -1.36 -1.36 0 0 0 16 MHz SPBRG value (decimal) KBAUD 129 64 32 21 10 4 1 0 9.615 19.230 38.461 58.823 111.111 250 NA NA 10 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 +0.16 +2.12 -3.55 0 - 103 51 25 16 8 3 - 9.615 18.939 39.062 56.818 125 NA 625 NA 7.
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PIC16C6X 12.1.1 set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge after the first falling edge of a x4 clock (Figure 12-4 and Figure 12-5). SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. If bit BRGH (TXSTA<2>) is clear (i.e.
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PIC16C6X FIGURE 12-6: RX PIN SAMPLING SCHEME (BRGH = 0 OR = 1) (PIC16C66/67) Start bit RX (RC7/RX/DT pin) Bit0 Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples  1997-2013 Microchip Technology Inc.
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PIC16C6X 12.2 USART Asynchronous Mode abled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit which is set when the TSR register is empty.
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PIC16C6X Steps to follow when setting up an Asynchronous Transmission: 5. 1. 6. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, then set bit BRGH. (Section 12.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 2. 3. 4. 7. Enable the transmission by setting bit TXEN, which will also set bit TXIF.
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PIC16C6X 12.2.2 possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG is still full, then the overrun error bit, OERR (RCSTA<1>) will be set. The word in the RSR register will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software.
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PIC16C6X 6. Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 12.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting enable bit CREN. TABLE 12-7: 7. 8. 9.
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PIC16C6X 12.3 USART Synchronous Master Mode Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 In Synchronous Master mode the data is transmitted in a half-duplex manner i.e., transmission and reception do not occur at the same time. When transmitting data the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>).
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PIC16C6X TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Address Name Bit 7 Bit 6 0Ch PIR1 PSPIF(1) (2) 18h RCSTA SPEN RX9 19h TXREG 8Ch PIE1 98h TXSTA 99h SPBRG Bit 5 Value on POR, BOR Value on all other Resets Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x USART Transmit Register 0000 0000 0000 0000 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE T
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PIC16C6X 12.3.2 Steps to follow when setting up Synchronous Master Reception: USART SYNCHRONOUS MASTER RECEPTION 1. Initialize the SPBRG register for the appropriate baud rate (Section 12.1). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set enable bit SREN.
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PIC16C6X FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.  1997-2013 Microchip Technology Inc.
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PIC16C6X 12.4 USART Synchronous Slave Mode Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Synchronous Slave Mode differs from Master Mode in the fact that the shift clock is supplied externally at the CK pin (instead of being supplied internally in master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 12.4.
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PIC16C6X TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 18h RCSTA 19h TXREG 8Ch PIE1 98h TXSTA 99h SPBRG USART Transmit Register (1) PSPIE CSRC (2) RCIE TXIE SSPIE CCP1IE TMR2
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PIC16C6X NOTES: DS30234E-page 122  1997-2013 Microchip Technology Inc.
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PIC16C6X 13.0 SPECIAL FEATURES OF THE CPU timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry.
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PIC16C6X FIGURE 13-2: CONFIGURATION WORD FOR PIC16C62/64/65 — — — — — — — — CP1 CP0 bit13 PWRTE WDTE FOSC1 FOSC0 bit0 Register: Address CONFIG 2007h bit 13-6: Unimplemented: Read as '1' bit 5-4: CP1:CP0: Code Protection bits 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 3: PWRTE: Power-up Timer Enable bit 1 = Power-up Timer enabled 0 = Power-up Timer disabled bit 2: WDTE: Wa
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PIC16C6X 13.2 Oscillator Configurations Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 13.2.1 OSCILLATOR TYPES The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC 13.2.
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PIC16C6X TABLE 13-1: CERAMIC RESONATORS PIC16C61 TABLE 13-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR FOR PIC16C61 Ranges Tested: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.
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PIC16C6X 13.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 13-6 shows implementation of a parallel resonant oscillator circuit.
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PIC16C6X 13.3 Reset Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The PIC16CXX differentiates between various kinds of reset: • • • • • Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (normal operation) Brown-out Reset (BOR) - Not on PIC16C61/62/ 64/65 The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 13-7, Table 13-8, and Table 13-9.
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PIC16C6X 13.4 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR) The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 13.4.3 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 13.4.1 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over.
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PIC16C6X 13.4.5 13.4.6 TIME-OUT SEQUENCE On power-up the time-out sequence is as follows: First a PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode, with the PWRT disabled, there will be no time-out at all. Figure 13-11, Figure 13-12, and Figure 13-13 depict time-out sequences on power-up.
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PIC16C6X TABLE 13-9: POR STATUS BITS AND THEIR SIGNIFICANCE FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 BOR TO 0 x 1 0 x 0 0 x x 1 0 x 1 1 0 1 1 0 1 1 u 1 1 1 Legend: x = unknown, u = unchanged PD 1 x 0 x 1 0 u 0 Power-on Reset Illegal, TO is set on a Power-on Reset Illegal, PD is set on a Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR reset during normal operation MCLR reset during SLEEP or interrupt wake-up from SLEEP TABLE 13-10: RESET CONDITION FOR SPECIAL REGISTERS ON PIC16C61/62/6
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PIC16C6X TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset MCLR Reset during: Brown-out – normal operation Reset – SLEEP WDT Reset Wake-up via interrupt or WDT Wake-up W 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu INDF 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 N/A N/A N/A TMR0 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu PCL 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
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PIC16C6X TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.
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PIC16C6X FIGURE 13-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 13-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 13-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30234E-page 134  1997-2013 Microchip Technolog
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PIC16C6X FIGURE 13-14: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 13-15: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD VDD D VDD 33k R 10k MCLR R1 MCLR C 40k PIC16CXX PIC16CXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the devices electrical specifications.
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PIC16C6X 13.5 Interrupts Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The PIC16C6X family has up to 11 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or global enable bit, GIE.
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PIC16C6X FIGURE 13-17: INTERRUPT LOGIC FOR PIC16C61 Wake-up (If in SLEEP mode) T0IF T0IE INTF INTE Interrupt to CPU RBIF RBIE GIE FIGURE 13-18: INTERRUPT LOGIC FOR PIC16C6X PSPIF PSPIE RCIF RCIE Wake-up (If in SLEEP mode) T0IF T0IE INTF INTE TXIF TXIE Interrupt to CPU RBIF RBIE SSPIF SSPIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts.
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PIC16C6X 13.5.1 INT INTERRUPT 13.5.2 TMR0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (Section 7.0). External interrupt on RB0/INT pin is edge triggered: either rising if edge select bit INTEDG (OPTION<6>) is set, or falling, if bit INTEDG is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set.
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PIC16C6X 13.6 Context Saving During Interrupts Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 13-1 stores and restores the STATUS and W registers. Example 13-2 stores and restores the STATUS, W, and PCLATH registers (Devices with paged program memory).
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PIC16C6X 13.7 Watchdog Timer (WDT) assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.
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PIC16C6X 13.8 Power-down Mode (SLEEP) Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, status bit PD (STATUS<3>) is cleared, status bit TO (STATUS<4>) is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
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PIC16C6X FIGURE 13-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) PC+1 PC+2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst
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PIC16C6X 14.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 14-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 14-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator.
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PIC16C6X TABLE 14-2: PIC16CXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to
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PIC16C6X 14.1 Instruction Descriptions ADDLW Add Literal and W ANDLW Syntax: [label] ADDLW Syntax: [label] ANDLW Operands: 0  k  255 Operands: 0  k  255 Operation: (W) + k  (W) Operation: (W) .AND. (k)  (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 k 111x kkkk kkkk AND Literal with W Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
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PIC16C6X BCF Bit Clear f Syntax: [label] BCF BTFSC Operands: Bit Test, Skip if Clear Syntax: [label] BTFSC f,b 0  f  127 0b7 Operands: 0  f  127 0b7 Operation: 0  (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: Description: 01 f,b 00bb bfff ffff Bit 'b' in register 'f' is cleared.
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PIC16C6X BTFSS Bit Test f, Skip if Set CALL Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0  f  127 0b<7 Operands: 0  k  2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1 TOS, k  PC<10:0>, (PCLATH<4:3>)  PC<12:11> Status Affected: None Encoding: Description: 01 Words: 1 Cycles: 1(2) Q Cycle Activity: If Skip: Example 11bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is executed.
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PIC16C6X CLRF Clear f Syntax: [label] CLRF Operands: 0  f  127 Operation: 00h  (f) 1Z Status Affected: Z Encoding: Description: 00 1 Cycles: 1 Example 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set. Words: Q Cycle Activity: CLRW f Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' CLRF [ label ] CLRW Operands: None Operation: 00h  (W) 1Z Status Affected: Z Encoding: 0001 0xxx xxxx W register is cleared.
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PIC16C6X COMF Complement f Syntax: [ label ] COMF Operands: DECFSZ f,d Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d 0  f  127 d  [0,1] Operands: 0  f  127 d  [0,1] Operation: (f)  (destination) Operation: Status Affected: Z (f) - 1  (destination); skip if result = 0 Status Affected: None Encoding: Description: 00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
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PIC16C6X GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0  k  2047 Operands: Operation: k  PC<10:0> PCLATH<4:3>  PC<12:11> 0  f  127 d  [0,1] Operation: (f) + 1  (destination) Status Affected: None Status Affected: Z Encoding: 10 GOTO k 1kkk kkkk kkkk Encoding: 00 INCF f,d 1010 dfff ffff Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>.
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PIC16C6X INCFSZ Increment f, Skip if 0 IORLW Syntax: [ label ] Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operands: 0  k  255 Operation: (W) .OR.
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PIC16C6X IORWF Inclusive OR W with f MOVLW Syntax: [ label ] Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operands: 0  k  255 Operation: (W) .OR.
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PIC16C6X NOP No Operation RETFIE Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS  PC, 1  GIE Status Affected: None Encoding: Description: 00 NOP 0000 0xx0 0000 Encoding: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example Return from Interrupt Q2 Q3 0000 0000 1001 Description: Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
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PIC16C6X RETLW Return with Literal in W RETURN Syntax: [ label ] Syntax: [ label ] Operands: 0  k  255 Operands: None Operation: k  (W); TOS  PC Operation: TOS  PC Status Affected: None Status Affected: RETLW k None Encoding: Encoding: 11 Description: 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
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PIC16C6X RLF Rotate Left f through Carry RRF Syntax: [ label ] Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operands: 0  f  127 d  [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: RLF 00 f,d 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register.
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PIC16C6X SLEEP Syntax: SUBLW [ label ] SLEEP Subtract W from Literal Syntax: [ label ] 0 k 255 SUBLW k Operands: None Operands: Operation: 00h  WDT, 0  WDT prescaler, 1  TO, 0  PD Operation: k - (W) W) Status Affected: C, DC, Z Encoding: 11 110x kkkk kkkk Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register. The power-down status bit, PD is cleared. Time-out status bit, TO is set.
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PIC16C6X SUBWF Subtract W from f SWAPF Syntax: [ label ] Syntax: [ label ] SWAPF f,d Operands: 0 f 127 d  [0,1] Operands: 0  f  127 d  [0,1] Operation: (f) - (W) destination) Operation: Status Affected: C, DC, Z (f<3:0>)  (destination<7:4>), (f<7:4>)  (destination<3:0>) Status Affected: None Encoding: Description: 00 1 Cycles: 1 Q1 Decode Example 1: 0010 dfff ffff Subtract (2’s complement method) W register from register 'f'.
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PIC16C6X XORLW Exclusive OR Literal with W XORWF Syntax: [label] Syntax: [label] Operands: 0  f  127 d  [0,1] Operands: XORLW k 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Encoding: Description: 11 Words: 1 Cycles: 1 Q Cycle Activity: Example: 1010 kkkk kkkk The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.0 ELECTRICAL CHARACTERISTICS FOR PIC16C61 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature ..............................................................................................................................
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.1 DC Characteristics: PIC16C61-04 (Commercial, Industrial, Extended) PIC16C61-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.2 DC Characteristics: DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.3 DC Characteristics: PIC16C61-04 (Commercial, Industrial, Extended) PIC16C61-20 (Commercial, Industrial, Extended) PIC16LC61-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.5 Timing Diagrams and Specifications FIGURE 15-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 15-2: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 15-1 for load conditions. TABLE 15-3: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 15-1 for load conditions. TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-5: TIMER0 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 TMR0 Note: Refer to Figure 15-1 for load conditions. TABLE 15-5: Parameter No. 40* TIMER0 EXTERNAL CLOCK REQUIREMENTS Sym Characteristic Tt0H T0CKI High Pulse Width Min No Prescaler With Prescaler 41* Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* Tt0P T0CKI Period No Prescaler With Prescaler * † Typ† Max Units Conditions 0.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C61 Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution while 'max' or 'min' represents (mean +3) and (mean -3) respectively where  is standard deviation.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD 8.0 5.0 R = 3.3k 4.5 R = 4.7k 7.0 4.0 6.0 R = 4.7k 5.0 3.0 Fosc (MHz) Fosc (MHz) 3.5 R = 10k 2.5 4.0 R = 10k 2.0 3.0 1.5 2.0 1.0 Cext = 300 pF, T = 25C 1.0 0.5 R = 100k R = 100k 0.0 3.0 3.5 4.0 4.5 5.0 5.5 0.0 3.0 6.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-6: TYPICAL IPD VS. VDD WATCHDOG TIMER ENABLED 25C FIGURE 16-7: MAXIMUM IPD VS. VDD WATCHDOG DISABLED 25 14 125C 12 20 10 IPD (A) IPD (A) 15 8 6 10 70C 5 2 0 3.0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 0C -40C -55C 6.0 VDD (Volts)  1997-2013 Microchip Technology Inc. DS30234E-page 171 Data based on matrix samples. See first page of this section for details.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-8: MAXIMUM IPD VS. VDD WATCHDOG ENABLED* FIGURE 16-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD 45 -55C -40C 40 2.00 1.80 IPD (A) 30 125C 25 VTH (Volts) 35 Max (-40C to 85C) 1.60 25C, Typ 1.40 1.20 Min (-40C to 85C) 1.00 20 0.80 15 0.60 2.5 0C 70C 85C 3.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 6.0 10 Data based on matrix samples. See first page of this section for details. 5 0 3.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD 4.5 VIH, Max (-40C to 85C) VIH, Typ (25C) 4.0 VIH, Min (-40C to 85C) VIH, VIL (Volts) 3.5 3.0 2.5 2.0 1.5 VIL, Max (-40C to 85C) 1.0 VIL, Typ (25C) VIL, Min (-40C to 85C) 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FIGURE 16-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) VS. VDD 3.6 Max (-40C to 85C) 3.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-12: TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 IDD (A) 1,000 100 1 10,000 100,000 1,000,000 100,000,000 10,000,000 Frequency (Hz) FIGURE 16-13: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -40 TO +85C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 IDD (A) Data based on matrix samples. See first page of this section for details.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-14: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -55 TO +125C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 IDD (A) 1,000 10 10,000 100,000 1,000,000 100,000,000 10,000,000 Frequency (Hz) FIGURE 16-15: WDT TIMER TIME-OUT PERIOD VS. VDD FIGURE 16-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR VS. VDD 50 9000 45 8000 40 7000 Max. -40C 6000 gm (A/V) WDT period (ms) 35 30 Max. 85C 5000 4000 25 Typ. 25C Max.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR VS. VDD FIGURE 16-19: IOH VS. VOH, VDD = 3V 0 225 -5 200 MIn. 85C Max. -40C 175 150 -10 IOH (mA) gm (A/V) Typ. 25C 125 100 Typ. 25C -15 MIn. 85C 75 -20 25 Max. -40C 0 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 -25 6.0 0 FIGURE 16-18: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR VS. VDD 0.5 1.0 1.5 VOH (Volts) 2.0 2.5 3.0 FIGURE 16-20: IOH VS.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-21: IOL VS. VOL, VDD = 3V FIGURE 16-22: IOL VS. VOL, VDD = 5V 90 35 80 Min @ -40C 30 Min @ -40C 70 25 60 Typ @ 25C Typ @ 25C IOL (mA) IOL (mA) 20 15 50 Min @ +85C 40 Min @ +85C 30 10 5 10 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOL (Volts) TABLE 16-2: VOL (Volts) INPUT CAPACITANCE* Pin Name RA port Typical Capacitance (pF) 18L PDIP 18L SOIC 5.0 4.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 178  1997-2013 Microchip Technology Inc.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C62/64 Absolute Maximum Ratings † Ambient temperature under bias...............................................................................................................-55°C to +85°C Storage temperature ..............................................................................................................................
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C62/64-04 (Commercial, Industrial) PIC16C62/64-10 (Commercial, Industrial) PIC16C62/64-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 - 6.0 5.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.2 DC Characteristics: DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.3 DC Characteristics: PIC16C62/64-04 (Commercial, Industrial) PIC16C62/64-10 (Commercial, Industrial) PIC16C62/64-20 (Commercial, Industrial) PIC16LC62/64-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.5 Timing Diagrams and Specifications FIGURE 17-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 17-2: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 17-1 for load conditions.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 17-1 for load conditions. TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSI/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 17-1 for load conditions. TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 54 53 Note: Refer to Figure 17-1 for load conditions. TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-7: PARALLEL SLAVE PORT TIMING (PIC16C64) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 17-1 for load conditions TABLE 17-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64) Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 17-1 for load conditions TABLE 17-8: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-9: I2C BUS START/STOP BITS TIMING SCL 91 93 92 90 SDA STOP Condition START Condition Note: Refer to Figure 17-1 for load conditions TABLE 17-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-10: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 17-1 for load conditions TABLE 17-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time Min Max Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 194  1997-2013 Microchip Technology Inc.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.0 ELECTRICAL CHARACTERISTICS FOR PIC16C62A/R62/64A/R64 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature ..............................................................................................................................
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.1 DC Characteristics: DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.2 DC Characteristics: PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.3 DC Characteristics: PIC16C62A/R62/64A/R64-04 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-10 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-20 (Commercial, Industrial, Extended) PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.5 Timing Diagrams and Specifications FIGURE 18-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 18-2: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 10 11 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 18-1 for load conditions.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 18-1 for load conditions. FIGURE 18-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 18-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 18-1 for load conditions. TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 18-1 for load conditions. TABLE 18-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Parameter Sym Characteristic No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-8: PARALLEL SLAVE PORT TIMING (PIC16C64A/R64) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 18-1 for load conditions TABLE 18-7: Parameter No. 62 63* 64 65* * † PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64A/R64) Sym Characteristic Min Typ† Max Units 20 — — ns 25 — — ns PIC16C64A/R64 20 — — ns PIC16LC64A.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 18-1 for load conditions TABLE 18-8: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-10: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 18-1 for load conditions TABLE 18-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 92 91 SDA In 110 109 109 SDA Out Note: Refer to Figure 18-1 for load conditions TABLE 18-10: I2C BUS DATA REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 210  1997-2013 Microchip Technology Inc.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C65 Absolute Maximum Ratings † Ambient temperature under bias...............................................................................................................-55°C to +85°C Storage temperature ..............................................................................................................................
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C65-04 (Commercial, Industrial) PIC16C65-10 (Commercial, Industrial) PIC16C65-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 - 6.0 5.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.2 DC Characteristics: DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.3 DC Characteristics: PIC16C65-04 (Commercial, Industrial) PIC16C65-10 (Commercial, Industrial) PIC16C65-20 (Commercial, Industrial) PIC16LC65-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. D100 Characteristic Capacitive Loading Specs on Output Pins OSC2 pin Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.5 Timing Diagrams and Specifications FIGURE 19-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 19-2: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 19-1 for load conditions. TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PAGE 219
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 19-1 for load conditions. TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 19-1 for load conditions. TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 19-1 for load conditions. TABLE 19-6: Parameter No. 50* 51* Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min With Prescaler 0.5TCY + 20 — — ns 10 — — ns PIC16LC65 20 — — ns 0.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-7: PARALLEL SLAVE PORT TIMING RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 19-1 for load conditions TABLE 19-7: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 19-1 for load conditions TABLE 19-8: Parameter No.
PAGE 224
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-9: I2C BUS START/STOP BITS TIMING SCL 91 93 92 90 SDA STOP Condition START Condition Note: Refer to Figure 19-1 for load conditions TABLE 19-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-10: I2C BUS DATA TIMING 103 102 100 101 SCL 106 90 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 19-1 for load conditions TABLE 19-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time Min Max Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Devce must operate at a minimum of 10 MHz 1.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 19-1 for load conditions TABLE 19-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter Sym No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.0 ELECTRICAL CHARACTERISTICS FOR PIC16C63/65A Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature ..............................................................................................................................
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.1 DC Characteristics: DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.2 DC Characteristics: PIC16LC63/65A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.3 DC Characteristics: PIC16C63/65A-04 (Commercial, Industrial, Extended) PIC16C63/65A-10 (Commercial, Industrial, Extended) PIC16C63/65A-20 (Commercial, Industrial, Extended) PIC16LC63/65A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2 Sym Min Typ Max Units Conditions † VDD-0.7 - - V VDD-0.7 - - V VDD-0.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.5 Timing Diagrams and Specifications FIGURE 20-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 20-2: Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 20-1 for load conditions. TABLE 20-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PAGE 235
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 20-1 for load conditions. FIGURE 20-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 20-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PAGE 236
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 20-1 for load conditions. TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PAGE 237
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 54 53 Note: Refer to Figure 20-1 for load conditions. TABLE 20-6: Parameter No.
PAGE 238
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-8: PARALLEL SLAVE PORT TIMING (PIC16C65A) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 20-1 for load conditions TABLE 20-7: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 20-1 for load conditions TABLE 20-8: Parameter No.
PAGE 240
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-10: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 20-1 for load conditions TABLE 20-9: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 20-1 for load conditions TABLE 20-10: I2C BUS DATA REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 20-1 for load conditions TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter No.
PAGE 243
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.0 ELECTRICAL CHARACTERISTICS FOR PIC16CR63/R65 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature ..............................................................................................................................
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16CR63/R65-04 (Commercial, Industrial) PIC16CR63/R65-10 (Commercial, Industrial) PIC16CR63/R65-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 5.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.2 DC Characteristics: PIC16LCR63/R65-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
PAGE 246
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.3 DC Characteristics: PIC16CR63/R65-04 (Commercial, Industrial) PIC16CR63/R65-10 (Commercial, Industrial) PIC16CR63/R65-20 (Commercial, Industrial) PIC16LCR63/R65-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 21.1 and Section 21.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PAGE 249
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.5 Timing Diagrams and Specifications FIGURE 21-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 21-2: Param No.
PAGE 250
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 21-1 for load conditions. TABLE 21-3: Param No.
PAGE 251
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 21-1 for load conditions. FIGURE 21-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 21-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PAGE 252
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 21-1 for load conditions. TABLE 21-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PAGE 253
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 21-1 for load conditions. TABLE 21-6: Param No.
PAGE 254
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-8: PARALLEL SLAVE PORT TIMING (PIC16CR65) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 21-1 for load conditions TABLE 21-7: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 21-1 for load conditions TABLE 21-8: Parameter No.
PAGE 256
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-10: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 21-1 for load conditions TABLE 21-9: Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 21-1 for load conditions TABLE 21-10: I2C BUS DATA REQUIREMENTS Parameter No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 21-1 for load conditions TABLE 21-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.0 ELECTRICAL CHARACTERISTICS FOR PIC16C66/67 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature ..............................................................................................................................
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.1 DC Characteristics: DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.2 DC Characteristics: PIC16LC66/67-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.3 DC Characteristics: PIC16C66/67-04 (Commercial, Industrial, Extended) PIC16C66/67-10 (Commercial, Industrial, Extended) PIC16C66/67-20 (Commercial, Industrial, Extended) PIC16LC66/67-04 (Commercial, Industrial) DC CHARACTERISTICS Param No.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 22.1 and Section 22.2 Sym Min Typ Max Units Conditions † VDD-0.7 - - V VDD-0.7 - - V VDD-0.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PAGE 265
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.5 Timing Diagrams and Specifications FIGURE 22-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 22-2: Param No.
PAGE 266
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 22-1 for load conditions. TABLE 22-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PAGE 267
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 22-1 for load conditions. FIGURE 22-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 22-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PAGE 268
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 22-1 for load conditions. TABLE 22-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PAGE 269
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 54 53 Note: Refer to Figure 22-1 for load conditions. TABLE 22-6: Parameter No.
PAGE 270
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-8: PARALLEL SLAVE PORT TIMING (PIC16C67) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 22-1 for load conditions TABLE 22-7: Parameter No.
PAGE 271
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-9: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSB SDO LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 22-1 for load conditions.
PAGE 272
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-11: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSB SDO LSB BIT6 - - - - - -1 77 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 22-1 for load conditions.
PAGE 273
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 TABLE 22-8: Parameter No.
PAGE 274
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-13: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 22-1 for load conditions TABLE 22-9: Parameter No.
PAGE 275
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-14: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 22-1 for load conditions TABLE 22-10: I2C BUS DATA REQUIREMENTS Parameter No.
PAGE 276
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 22-1 for load conditions TABLE 22-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter No.
PAGE 277
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR: PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64, PIC16C65A, PIC16C66, PIC16C67 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range).
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-3: TYPICAL IPD vs. VDD @ 25C (WDT ENABLED, RC MODE) FIGURE 23-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 22 pF, T = 25C 6.0 25 5.5 5.0 4.5 Fosc(MHz) IPD(A) 20 15 10 R = 5k 4.0 3.5 3.0 R = 10k 2.5 2.0 5 1.5 1.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 2.5 VDD(Volts) FIGURE 23-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE) 35 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 0C Cext = 100 pF, T = 25C 2.4 2.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE) FIGURE 23-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) 1400 1200 30 25 Device NOT in Brown-out Reset 800 20 600 400 200 0 2.5 IPD(A) IPD(A) 1000 Device in Brown-out Reset 15 10 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 5 6.0 0 2.5 The shaded region represents the built-in hysteresis of the brown-out reset circuitry.
PAGE 280
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V 1400 IDD(A) 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency(MHz) 3.5 4.0 4.5 Shaded area is beyond recommended range FIGURE 23-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40C TO 85C) 2000 6.0V 1800 5.5V 5.0V 1600 4.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(A) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz) FIGURE 23-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO 85C) 1600 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(A) 3.5V 3.0V 800 2.
PAGE 282
PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V IDD(A) 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 23-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO 85C) 1200 6.0V 5.5V 5.0V 4.5V 4.0V 800 3.5V IDD(A) Data based on matrix samples. See first page of this section for details. 1000 3.0V 600 2.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE) FIGURE 23-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD 600 4.0 500 3.5 3.0 gm(mA/V) 4.0V 400 IDD(A) Max -40C 5.0V 3.0V 300 200 2.5 Typ 25C 2.0 Min 85C 1.5 1.0 100 0.5 100 pF TABLE 23-1: 0.0 3.0 300 pF RC OSCILLATOR FREQUENCIES 300 pF 5k 4.12 MHz ± 1.4% 10k 2.35 MHz ± 1.4% 100k 268 kHz ± 1.1% 5.5 6.0 6.5 7.0 80 70 60 1.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C) FIGURE 23-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25C) 3.5 70 3.0 60 50 Startup Time(ms) Startup Time(Seconds) 2.5 2.0 32 kHz, 33 pF/33 pF 1.5 1.0 40 200 kHz, 68 pF/68 pF 30 200 kHz, 47 pF/47 pF 20 1 MHz, 15 pF/15 pF 10 0.5 4 MHz, 15 pF/15 pF 200 kHz, 15 pF/15 pF 0.0 2.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 6.0 4.0 4.5 VDD(Volts) 5.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25°C) FIGURE 23-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25°C) 1800 1600 6.0V 1400 5.5V 120 100 5.0V 1200 4.5V 1000 4.0V 60 40 20 0 0 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V IDD(A) IDD(A) 80 3.5V 800 3.0V 600 2.5V 400 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 23-26: MAXIMUM IDD vs.
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PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25°C) 7.0 FIGURE 23-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40°C TO 85°C) 7.0 6.0 6.0 5.0 IDD(mA) IDD(mA) 5.0 4.0 3.0 2.0 1.0 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4.0 3.0 2.0 1.0 4 6 8 10 12 Frequency(MHz) 14 16 18 20 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4 6 8 10 12 14 16 18 20 Data based on matrix samples. See first page of this section for details.
PAGE 287
PIC16C6X 24.0 PACKAGING INFORMATION 24.1 18-Lead Plastic Dual In-line (300 mil) (P) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  E1 C E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 e1 B A1 A2 A D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max  0 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.
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PIC16C6X 24.2 28-Lead Plastic Dual In-line (300 mil) (SP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1  E C eA eB Pin No. 1 Indicator Area B2 D B1 S Base Plane Seating Plane L Detail A B3 A1 A2 A e1 B Detail A D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max Inches Notes Min Max  0 10 0 10 A A1 A2 B B1 B2 B3 C D D1 E E1 e1 eA eB L N S 3.632 0.381 3.
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PIC16C6X 24.3 40-Lead Plastic Dual In-line (600 mil) (P) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1  E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Min Max  0 10 0 10 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.175 0.355 1.270 0.203 51.181 48.
PAGE 290
PIC16C6X 24.4 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e B h x 45 N Index Area E H  C Chamfer h x 45 L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max  0 8 0 8 A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.
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PIC16C6X 24.5 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e B h x 45 N Index Area E H  C Chamfer h x 45 L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Inches Symbol Min Max Min Max  0 8 0 8 A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 17.703 7.416 1.270 10.007 0.
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PIC16C6X 24.6 18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  E1 C E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A3 A e1 B A2 D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Min Max  0 10 0 10 A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 — 0.381 3.
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PIC16C6X 24.7 28-Lead Ceramic CERDIP Dual In-line with Window (300 mil)) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 E  C Pin No. 1 Indicator Area eA eB D D1 Base Plane Seating Plane L B1 A1 A2 A e1 B D2 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Min Max  0 10 0 10 A A1 A2 B B1 C D D2 E E1 e eA eB L N D1 3.30 0.38 2.92 0.35 1.
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PIC16C6X 24.8 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 E  C Pin No. 1 Indicator Area eA eB D S S1 Base Plane Seating Plane L B1 A1 A3 A A2 e1 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol Min Max  0 A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 4.318 0.381 3.810 3.810 0.355 1.270 0.203 51.
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PIC16C6X 24.9 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N C E1 E eA eB  Pin #1 Indicator Area D S1 S Base Plane Seating Plane L B1 A3 A2 A A1 e1 B D1 Package Group: Ceramic Side Brazed Dual In-Line (CER) Millimeters Inches Symbol  A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 Min Max 0 3.937 1.016 2.921 1.930 0.406 1.
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PIC16C6X 24.10 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N Index area E H  C L 1 2 3 B e A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Inches Symbol Min Max Min Max  0 8 0 8 A A1 B C D E e H L N CP 1.730 0.050 0.250 0.130 10.070 5.200 0.650 7.650 0.550 28 - 1.990 0.210 0.380 0.220 10.
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PIC16C6X 24.11 44-Lead Plastic Leaded Chip Carrier (Square) (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D -A- D1 -D- 3 -F- 0.812/0.661 N Pics .032/.026 1.27 .050 2 Sides 0.177 .007 S B D-E S -HA A1 3 D3/E3 D2 0.38 .015 3 -G- 8 F-G S 0.177 .007 S B A S 2 Sides 9 0.101 Seating .004 Plane D -C- 4 E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.254 .010 Max 2 0.
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PIC16C6X 24.12 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 4 D D1 5 0.20 M C A-B S D S 0.20 M H A-B S D S 7 0.20 min. 0.05 mm/mm A-B D3 0.13 R min. Index area 6 9 PARTING LINE b 0.13/0.30 R  L C E3 E1 E 1.60 Ref. 0.20 M C A-B S D S 4 TYP 4x 10 e 0.20 M H A-B S B D S 5 7 0.
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PIC16C6X 24.13 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 1.0ø (0.039ø) Ref. Pin#1 2 11/13(4x) Pin#1 2 E 0 Min E1  11/13(4x) Detail B e 3.0ø (0.118ø) Ref. Option 1 (TOP side) A1 A2 Detail B Detail A R1 0.08 Min R 0.08/0.20 Option 2 (TOP side) A L Base Metal b Lead Finish L c 1.00 Ref. Gage Plane 0.
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PIC16C6X 24.14 Package Marking Information 18-Lead PDIP Example MMMMMMMMMMMMM XXXXXXXXXXXXXXXX PIC16C61-04/P AABBCDE 9450CBA 18-Lead SOIC Example MMMMMMMMMM XXXXXXXXXXXX XXXXXXXXXXXX PIC16C61 -20/SO AABBCDE 9449CBA 18-Lead CERDIP Windowed Example MMMMMM XXXXXXXX PIC16C61 /JW 9440CBT AABBCDE 28-Lead PDIP (.300 MIL) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX PIC16C63-04I/SP AABBCAE Legend: MM...M XX...
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PIC16C6X Package Marking Information (Cont’d) 28-Lead SOIC Example MMMMMMMMMMMMMMMMMMXX XXXXXXXXXXXXXXXXXXXX PIC16C62-20/S0111 AABBCAE 9515SBA 28-Lead CERDIP Skinny Windowed Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC16C62/JW AABBCDE 9517SBT 28-Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX XXXXXXXXXXX PIC16C66/JW AABBCDE 28-Lead SSOP 9517CAT Example XXXXXXXXXXXX XXXXXXXXXXXX PIC16C62 20I/SS025 AABBCAE 9517SBP Example 40-Lead PDIP MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXX
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PIC16C6X Package Marking Information (Cont’d) 40-Lead CERDIP Windowed Example PIC16C67/JW MMMMMMMMM XXXXXXXXXXX XXXXXXXXXXX 9450CAT AABBCDE 44-Lead PLCC Example MMMMMMMM XXXXXXXXXX PIC16C64 -20/L XXXXXXXXXX AABBCDE 9442CAN Example 44-Lead MQFP MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE PIC16C64 -04/PQ 9444CAP 44-Lead TQFP Example MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE Legend: Note: PIC16C64A -10/TQ AABBCDE MM...M XX...
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PIC16C6X APPENDIX A: MODIFICATIONS APPENDIX B: COMPATIBILITY The following are the list of modifications over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before).
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PIC16C6X APPENDIX C: WHAT’S NEW APPENDIX D: WHAT’S CHANGED Added PIC16CR63 and PIC16CR65 devices. Minor changes, spelling and grammatical changes. Added PIC16C66 and PIC16C67 devices. The PIC16C66/67 devices have 368 bytes of data memory distributed in 4 banks and 8K of program memory in 4 pages. These two devices have an enhanced SPI that supports both clock phase and polarity. The USART has been enhanced. Divided SPI section into SPI for the PIC16C66/67 (Section 11.
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PIC16C6X APPENDIX F: PIC16/17 MICROCONTROLLERS F.
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PIC16C6X F.3 PIC16C15X Family of Devices PIC16C154 Clock Memory PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 20 20 20 20 20 20 EPROM Program Memory (x12 words) 512 — 1K — 2K — ROM Program Memory (x12 words) — 512 — 1K — 2K RAM Data Memory (bytes) 25 25 25 25 73 73 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 12 12 Voltage Range (Volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.
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PIC16C6X F.5 PIC16C55X Family of Devices PIC16C556(1) PIC16C554 Clock Memory 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K Data Memory (bytes) 80 80 128 Timer Module(s) TMR0 TMR0 TMR0 — — — — — — Peripherals Comparators(s) Internal Reference Voltage Features PIC16C558 Maximum Frequency of Operation (MHz) Interrupt Sources 3 3 3 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.
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PIC16C6X F.
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PIC16C6X F.8 PIC16C8X Family of Devices PIC16F83 Maximum Frequency of Operation (MHz) Clock Memory Peripherals Features PIC16CR83 10 10 PIC16F84 10 PIC16CR84 10 Flash Program Memory 512 — 1K — EEPROM Program Memory — — — — ROM Program Memory — 512 — 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 Timer Module(s) TMR0 TMR0 TMR0 TMR0 Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.
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PIC16C6X F.
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PIC16C6X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55.
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PIC16C6X NOTES: DS30234E-page 312  1997-2013 Microchip Technology Inc.
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PIC16C6X INDEX Numerics 9-bit Receive Enable bit, RX9 ........................................... 106 9-bit Transmit Enable bit, TX9 .......................................... 105 9th bit of received data, RX9D .......................................... 106 9th bit of transmit data, TX9D ........................................... 105 A Absolute Maximum Ratings .............................. 163, 183, 199, 215, 231, 247, 263 ACK.....................................................................
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PIC16C6X Clearing Interrupts............................................................... 53 Clock Polarity Select bit, CKP ....................................... 85, 90 Clock Polarity, SPI Mode .................................................... 87 Clock Source Select bit, CSRC......................................... 105 Clocking Scheme ................................................................ 18 Code Examples Changing Between Capture Prescalers ......................
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PIC16C6X Transfer Acknowledge ................................................ 96 Transmission............................................................. 102 ID Locations ...................................................................... 142 IDLE_MODE ..................................................................... 104 In-circuit Serial Programming............................................ 142 INDF......................................................
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PIC16C6X OSC1/CLKIN............................................................... 16 OSC2/CLKOUT........................................................... 16 PORTA........................................................................ 52 PORTB........................................................................ 54 PORTC ....................................................................... 55 PORTD ....................................................................... 57 PORTE.......................
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PIC16C6X Registers CCP1CON Diagram .............................................................. 78 Section ................................................................ 78 Summary .................................... 24, 26, 28, 30, 32 CCP2CON Diagram .............................................................. 78 Section ................................................................ 78 Summary ................................................ 26, 30, 32 CCPR1H Summary ..............................
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PIC16C6X TXSTA Diagram ............................................................ 105 Section .............................................................. 105 Summary....................................................... 31, 33 W................................................................................... 9 Special Function Registers, Initialization Conditions ................................................................. 132 Special Function Registers, Reset Conditions ..........
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PIC16C6X Overview ............................................................. 63 Prescaler............................................................. 72 Read/Write in Asynchronous Counter Mode ...... 73 Section ................................................................ 71 Synchronizing with External Clock...................... 72 Timer Mode......................................................... 72 TMR1 Register Pair ............................................ 71 Timer2 Block Diagram ...........
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PIC16C6X I2C Bus Start/Stop Bits...................................... 244 Oscillator Start-up Timer ................................... 239 Parallel Slave Port ............................................ 242 Power-up Timer ................................................ 239 Reset................................................................. 239 SPI Mode .......................................................... 243 Timer0............................................................... 240 Timer1.......
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PIC16C6X TMR0 .................................................... 24, 26, 28, 30, 32, 34 TMR0 Clock Source Select bit, T0CS ................................. 36 TMR0 Interrupt .................................................................... 65 TMR0 Overflow Interrupt Enable bit, T0IE .......................... 37 TMR0 Overflow Interrupt Flag bit, T0IF .............................. 37 TMR0 Prescale Selection Table ......................................... 36 TMR0 Source Edge Select bit, T0SE...........
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PIC16C6X LIST OF EQUATION AND EXAMPLES Figure 4-15: Example 3-1: Instruction Pipeline Flow ............................. 18 Example 4-1: Call of a Subroutine in Page 1 from Page 0 ................................................ 49 Example 4-2: Indirect Addressing ..................................... 49 Example 5-1: Initializing PORTA....................................... 51 Example 5-2: Initializing PORTB....................................... 53 Example 5-3: Initializing PORTC ........................
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PIC16C6X Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 11-8: Figure 11-9: Figure 11-10: Figure 11-11: Figure 11-12: Figure 11-13: Figure 11-14: Figure 11-15: Figure 11-16: Figure 11-17: Figure 11-18: Figure 11-19: Figure 11-20: Figure 11-21: Figure 11-22: Figure 11-23: Figure 11-24: Figure 11-25: Figure 11-26: Figure 11-27: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8: Figure 12-9: Figure 12-10: Figure 12-11: F
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PIC16C6X Figure 17-10: VIH, VIL of MCLR, T0CKI and OSC1 (in RC Mode) vs. VDD ............................... 177 Figure 17-11: VTH (Input Threshold Voltage) of OSC1 Input (in XT, HS, and LP Modes) vs. VDD ............................ 177 Figure 17-12: Typical IDD vs. Frequency (External Clock, 25C) .............................. 178 Figure 17-13: Maximum IDD vs. Frequency (External Clock, -40 to +85C)................. 178 Figure 17-14: Maximum IDD vs. Frequency (External Clock, -55 to +125C)...........
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PIC16C6X Figure 23-12: Figure 23-13: Figure 23-14: Figure 23-15: Figure 23-16: Figure 24-1: Figure 24-2: Figure 24-3: Figure 24-4: Figure 24-5: Figure 24-6: Figure 24-7: Figure 24-8: Figure 24-9: Figure 24-10: Figure 24-11: Figure 24-12: Figure 24-13: Figure 24-14: Figure 24-15: Figure 24-16: Figure 24-17: Figure 24-18: Figure 24-19: Figure 24-20: Figure 24-21: Figure 24-22: Figure 24-23: Figure 24-24: Figure 24-25: Figure 24-26: Figure 24-27: Figure 24-28: SPI Slave Mode Timing (CKE = 1) ...........
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PIC16C6X LIST OF TABLES Table 12-2: Table 1-1: Table 3-1: Table 3-2: Table 12-3: Table 12-4: Table 3-3: Table 4-1: Table 4-2: Table 4-3: Table 4-4: Table 4-5: Table 4-6: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 5-8: Table 5-9: Table 5-10: Table 5-11: Table 5-12: Table 5-13: Table 7-1: Table 8-1: Table 8-2: Table 9-1: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 10-5: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 11-5: Table 12-1: PIC16C6X Famil
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PIC16C6X Table 18-1: Table 18-2: Table 18-3: Table 18-4: Table 18-5: Table 18-6: Table 18-7: Table 18-8: Table 18-9: Table 18-10: Table 19-1: Table 19-2: Table 19-3: Table 19-4: Table 19-5: Table 19-6: Table 19-7: Table 19-8: Table 19-9: Table 19-10: Table 20-1: Table 20-2: Table 20-3: Table 20-4: Table 20-5: Table 20-6: Table 20-7: Table 20-8: Table 20-9: Table 20-10: Table 20-11: Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) ........
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PIC16C6X Table 23-5: Table 23-6: Table 23-7: Table 23-8: Table 23-9: Table 23-10: Table 23-11: Table 23-12: Table 24-1: Table 24-2: Table E-1: Timer0 and Timer1 External Clock Requirements ................................. 272 Capture/Compare/PWM Requirements (CCP1 and CCP2) ............. 273 Parallel Slave Port Requirements (PIC16C67) 274 SPI Mode Requirements........................... 277 I2C Bus Start/Stop Bits Requirements ........................................... 278 I2C Bus Data Requirements .....
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PIC16C6X ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts.
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PIC16C6X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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PIC16C6X PIC16C6X Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO.
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PIC16C6X DS30234E-page 332  1997-2013 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.