Datasheet

PIC16C63A/65B/73B/74B
DS30605D-page 92  1998-2013 Microchip Technology Inc.
ADCON0 63A 65B 73B 74B 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
TRISA 63A 65B 73B 74B --11 1111 --11 1111 --uu uuuu
TRISB 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
TRISC 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
TRISD
63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu
TRISE
63A 65B 73B 74B 0000 -111 0000 -111 uuuu -uuu
PIE1
63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu
63A 65B 73B 74B 0-00 0000 0-00 0000 u-uu uuuu
63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu
63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
PIE2 63A 65B 73B 74B ---- ---0 ---- ---0 ---- ---u
PCON
63A 65B 73B 74B
---- --0q
(3)
---- --uu ---- --uu
PR2 63A 65B 73B 74B 1111 1111 1111 1111 1111 1111
SSPADD 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu
TXSTA 63A 65B 73B 74B 0000 -010 0000 -010 uuuu -uuu
SPBRG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu
ADCON1
63A 65B 73B 74B ---- -000 ---- -000 ---- -uuu
TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset
Brown-out Reset
MCLR
Resets
WDT Reset
Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 13-5 for RESET value for specific condition.