Datasheet

PIC16C63A/65B/73B/74B
DS30605D-page 62  1998-2013 Microchip Technology Inc.
10.3.1.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W
bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK
) pulse is given. An overflow con-
dition is defined as any situation where a received byte
in SSPBUF is overwritten by the next received byte
before it has been read. An overflow has occurred
when:
a) The Buffer Full flag bit, BF(SSPSTAT<0>) was
set, indicating that the byte in SSPBUF was
waiting to be read when another byte was
received. This sets the SSPOV flag.
b) The overflow flag, SSPOV (SSPCON1<6>) was
set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 10-6: I
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1SDA
SCL
12
3
4
5
6
7
8
9
12
3
4
56
7
89
123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full
Cleared in software
SSPBUF register is read
ACK
Receiving Data
Receiving Data
D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Address
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent