Datasheet

1998-2013 Microchip Technology Inc. DS30605D-page 59
PIC16C63A/65B/73B/74B
FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7
bit6 bit5
bit4
bit3
bit2
bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
PSPIF
(1)
ADIF
(2)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1
PSPIE
(1)
ADIE
(2)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA
PORTA Data Direction register --11 1111 --11 1111
94h SSPSTAT SMP CKE
D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.