Datasheet
PIC16C63A/65B/73B/74B
DS30605D-page 18 1998-2013 Microchip Technology Inc.
Bank 1
80h INDF
(4)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL
(4)
Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS
(4)
IRP
(2)
RP1
(2)
RP0 TO PD ZDCC0001 1xxx 000q quuu
84h FSR
(4)
Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA
— — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction register 1111 1111 1111 1111
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
88h TRISD
(5)
PORTD Data Direction register 1111 1111 1111 1111
89h TRISE
(5)
IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
8Ah PCLATH
(1,4)
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON
(4)
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE
(5)
ADIE
(6)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2
— — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I
2
C mode) Address register 0000 0000 0000 0000
94h SSPSTAT — —D/A PSR/WUA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1
(6)
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RESETS include external RESET through MCLR
and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.