Datasheet

PIC16C63A/65B/73B/74B
DS30605D-page 136  1998-2013 Microchip Technology Inc.
FIGURE 16-18: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 16-19: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 16-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 16-4 for load conditions.
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
120* TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC16CXX — — 80 ns
PIC16LCXX — — 100 ns
121* Tckrf Clock out rise time and fall
time (Master mode)
PIC16CXX — — 45 ns
PIC16LCXX — — 50 ns
122* Tdtrf Data out rise time and fall time PIC16CXX — — 45 ns
PIC16LCXX — — 50 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note: Refer to Figure 16-4 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
125* TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK  (DT setup
time)
15 — — ns
126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.